Systems, methods, and apparatuses for tile store
US-12536020-B2 · Jan 27, 2026 · US
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Yanover Igor patents
Yanover Igor is listed as an inventor on 77 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Yanover Igor |
| Total patents | 77 |
| First publication | Mar 3, 2015 |
| Latest publication | Jan 27, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
US-2025117222-A1 · Apr 10, 2025 · US
Apparatuses, methods, and systems toprecisely monitor memory store accesses
US-12271735-B2 · Apr 8, 2025 · US
Systems, methods, and apparatuses for tile load
US-2025004716-A1 · Jan 2, 2025 · US
Systems, methods, and apparatuses for tile load, multiplication and accumulation
US-12182571-B2 · Dec 31, 2024 · US
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
US-12147804-B2 · Nov 19, 2024 · US
Systems, methods, and apparatuses for matrix operations
US-12106100-B2 · Oct 1, 2024 · US
Apparatus and method for power virus protection in a processor
US-12099597-B2 · Sep 24, 2024 · US
Systems, methods, and apparatuses for tile store
US-2024256276-A1 · Aug 1, 2024 · US
Apparatuses, methods, and systems to accelerate store processing
US-2024211262-A1 · Jun 27, 2024 · US
Recent patents
Latest publications not already listed above.
Systems, methods, and apparatuses for matrix operations
US-2024192954-A1 · Jun 13, 2024 · US
Systems, methods, and apparatuses for tile store
US-11977886-B2 · May 7, 2024 · US
Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits
US-11966334-B2 · Apr 23, 2024 · US
Apparatuses, methods, and systems to precisely monitor memory store accesses
US-11915000-B2 · Feb 27, 2024 · US
Apparatus and method for power virus protection in a processor
US-2024061928-A1 · Feb 22, 2024 · US
Apparatus and method for power virus protection in a processor
US-11809549-B2 · Nov 7, 2023 · US
Systems, methods, and apparatuses for tile store
US-11714642-B2 · Aug 1, 2023 · US
Systems, methods, and apparatuses for tile load
US-2023236833-A1 · Jul 27, 2023 · US
Memory tagging apparatus and method
US-11693785-B2 · Jul 4, 2023 · US
Restricted speculative execution mode to prevent observable side effects
US-11681533-B2 · Jun 20, 2023 · US
Apparatuses, methods, and systems to precisely monitor memory store accesses
US-2023176870-A1 · Jun 8, 2023 · US
Memory tagging metadata manipulation
US-11656998-B2 · May 23, 2023 · US
Apparatuses, methods, and systems to precisely monitor memory store accesses
US-2023082290-A1 · Mar 16, 2023 · US
Hardware for split data translation lookaside buffers
US-11580031-B2 · Feb 14, 2023 · US
Systems, methods, and apparatuses for tile load
US-11567765-B2 · Jan 31, 2023 · US
Apparatus and method for store pairing with reduced hardware requirements
US-11544062-B2 · Jan 3, 2023 · US
Systems, methods, and apparatuses for tile store
US-2022291927-A1 · Sep 15, 2022 · US
Systems, methods, and apparatuses for tile store
US-2022291926-A1 · Sep 15, 2022 · US
Apparatuses, methods, and systems to precisely monitor memory store accesses
US-11392380-B2 · Jul 19, 2022 · US
Memory tagging apparatus and method
US-11392503-B2 · Jul 19, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 77 |
| Raikin Shlomo | 3 |
| Shwartsman Stanislav | 3 |
| Yanover Igor | 3 |
| Sperber Zeev | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30043 | 44 |
| G06F9/30145 | 42 |
| G06F9/30038 | 34 |
| G06F9/30036 | 34 |
| G06F9/3836 | 31 |