Memory tagging metadata manipulation

Patent metadata

Field	Value
Publication number	US-11656998-B2
Application number	US-201916729371-A
Country	US
Kind code	B2
Filing date	Dec 28, 2019
Priority date	Dec 28, 2019
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

First claim

What is claimed is:

1. A processor comprising:
execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and
address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein when the first address pointer is to be translated with metadata processing, the address translation circuitry to:
access a set of one or more address translation tables to translate the first address pointer to a first physical address,
perform a lookup in a memory metadata table to identify a memory metadata value associated with a first physical address range including the first physical address,
determine a pointer metadata value associated with the first address pointer, and
compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition,
wherein when the comparison results in a validation of the memory access request, then return the first physical address responsive to the memory access request, and
wherein the processor has an instruction set architecture in which one or more dedicated memory metadata manipulation instructions are the only instructions through which memory metadata can be manipulated.

2. The processor of claim 1 , wherein the memory metadata value comprises a tag value associated with the physical address range.

3. The processor of claim 1 , wherein the memory metadata table is in a linear address space of the processor.

4. The processor of claim 1 , wherein the memory metadata value is hidden from software.

5. The processor of claim 1 , wherein the one or more dedicated memory metadata manipulation instructions includes an instruction to write a first number of bits of memory metadata, wherein execution of the instruction includes locking a second number of memory metadata bit locations until writing is complete, and wherein the second number is greater than the first number.

6. The processor of claim 1 , wherein the one or more dedicated memory metadata manipulation instructions includes an instruction to attach a metadata value to a second range of memory having a size greater than the first range.

7. A method comprising:
generating a system memory access request having a first address pointer responsive to execution, by a processor, of at least one instruction;
determining whether to translate the first address pointer with or without metadata processing; and
translating the first address pointer with metadata processing, wherein translating the first address pointer with metadata processing includes:
accessing a set of one or more address translation tables to translate the first address pointer to a first physical address,
performing a lookup in a memory metadata table to identify a memory metadata value associated with a physical memory range including the first physical address,
determining a pointer metadata value associated with the first address pointer,
comparing the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, and
returning the first physical address in response to a validation,
wherein the processor has an instruction set architecture in which one or more dedicated memory metadata manipulation instructions are the only instructions through which memory metadata can be manipulated.

8. The method of claim 7 , wherein the memory metadata value comprises a tag value associated with the physical address range.

9. The method of claim 7 , wherein the memory metadata table is in a linear address space of the processor.

10. The method of claim 7 , wherein the memory metadata value is hidden from software.

11. The method of claim 7 , wherein the one or more dedicated memory metadata manipulation instructions includes an instruction to write a first number of bits of memory metadata, wherein execution of the instruction includes locking a second number of memory metadata bit locations until writing is complete, and wherein the second number is greater than the first number.

12. The method of claim 7 , wherein the one or more dedicated memory metadata manipulation instructions includes an instruction to attach a metadata value to a second range of memory having a size greater than the first range.

13. A system comprising:
a system memory; and
a processor comprising:
execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and
address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein when the first address pointer is to be translated with metadata processing, the address translation circuitry to:
access a set of one or more address translation tables to translate the first address pointer to a first physical address,
perform a lookup in a memory metadata table to identify a memory metadata value associated with a first physical address range including the first physical address,
determine a pointer metadata value associated with the first address pointer, and
compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition,
wherein when the comparison results in a validation of the memory access request, then return the first physical address responsive to the memory access request, and
wherein the processor has an instruction set architecture in which one or more dedicated memory metadata manipulation instructions are the only instructions through which memory metadata can be manipulated.

14. The system of claim 13 , wherein the memory metadata value comprises a tag value associated with the physical address range.

15. The system of claim 13 , wherein the memory metadata table is in a linear address space of the processor.

16. The system of claim 13 , wherein the one or more dedicated memory metadata manipulation instructions includes an instruction to write a first number of bits of memory metadata, wherein execution of the instruction includes locking a second number of memory metadata bit locations until writing is complete, and wherein the second number is greater than the first number.

17. The system of claim 13 , wherein the one or more dedicated memory metadata manipulation instructions includes an instruction to attach a metadata value to a second range of memory having a size greater than the first range.

Assignees

• Intel Corp

Inventors

• Gabor Ron
• Perla Enrico
• Sade Raanan
• Yanover Igor
• Stark Tomer

Classifications

• G06F2212/7209

  Validity control, e.g. using flags, time stamps or sequence numbers · CPC title

• G06F12/1054

  the data cache being concurrently physically addressed · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title