Systems, methods, and apparatuses for tile store

Patent metadata

Field	Value
Publication number	US-11714642-B2
Application number	US-202217706428-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Mar 20, 2017
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.

First claim

We claim:

1. An apparatus comprising:
decode circuitry to decode a single instruction having fields for an opcode to indicate execution circuitry is to save a context state to memory, wherein the context state is to include multidimensional matrix data of tiles according to two configuration bits, a first configuration bit to correspond to configuration data loaded in a tile configuration and the second configuration bit to correspond to matrix data; and
execution circuitry to execute the decoded single instruction to store the context state to memory.

2. The apparatus of claim 1 , wherein the two configuration bits are located in a control register.

3. The apparatus of claim 1 , wherein the execution circuitry is a part of an accelerator.

4. The apparatus of claim 1 , wherein the execution circuitry is a part of a processor.

5. The apparatus of claim 1 , wherein the execution circuitry is further to write zeros beyond a specified number of rows of the matrix data of the tiles.

6. The apparatus of claim 1 , wherein the matrix data of the tiles is to include garbage data in areas that are not configured for use in tile operations.

7. The apparatus of claim 1 , wherein the tiles are a plurality of registers configured to represent a matrix.

8. A method comprising:
decoding a single instruction having fields for an opcode to indicate execution circuitry is to save a context state to memory, wherein the context state is to include multidimensional matrix data of tiles according to two configuration bits, a first configuration bit to correspond to configuration data loaded in a tile configuration and the second configuration bit to correspond to matrix data; and
executing the decoded single instruction to store the context state to memory.

9. The method of claim 8 , wherein the two configuration bits are located in a control register.

10. The method of claim 8 , wherein a size of each data element of the matrix data is a doubleword.

11. The method of claim 8 , wherein a size of each data element of the matrix data is a word.

12. The method of claim 8 , wherein the executing is further to write zeros beyond a specified number of rows of the matrix data of the tiles.

13. The method of claim 8 , wherein the matrix data of the tiles is to include garbage data in areas that are not configured for use in tile operations.

14. The method of claim 8 , wherein the tiles are a plurality of registers configured to represent a matrix.

15. A non-transitory machine-readable medium storing an instruction which causes an apparatus to perform a method, the method comprising:
decoding a single instruction having fields for an opcode to indicate execution circuitry is to save a context state to memory, wherein the context state is to include multidimensional matrix data of tiles according to two configuration bits, a first configuration bit to correspond to configuration data loaded in a tile configuration and the second configuration bit to correspond to matrix data; and
executing the decoded single instruction to store the context state to memory.

16. The non-transitory machine-readable medium of claim 15 , wherein the two configuration bits are located in a control register.

17. The non-transitory machine-readable medium of claim 15 , wherein the executing is further to write zeros beyond a specified number of rows of the matrix data of the tiles.

18. The non-transitory machine-readable medium of claim 15 , wherein the matrix data of the tiles is to include garbage data in areas that are not configured for use in tile operations.

19. The non-transitory machine-readable medium of claim 15 , wherein the tiles are a plurality of registers configured to represent a matrix.

Assignees

• Intel Corp

Inventors

• Valentine Robert
• Adelman Menachem
• Ould-Ahmed-Vall Elmoustapha
• Toll Bret L
• Girkar Milind B
• Sperber Zeev
• Charney Mark J
• Rappoport Rinat
• Corbal Jesus
• Shwartsman Stanislav
• Yanover Igor
• Heinecke Alexander F
• Ziv Barukh
• Baum Dan
• Gebil Yuri

Classifications

• G06F2212/455

  Image or video data · CPC title

• G06F2212/454

  Vector or matrix data · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title