Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

Patent metadata

Field	Value
Publication number	US-11966334-B2
Application number	US-202117146440-A
Country	US
Kind code	B2
Filing date	Jan 11, 2021
Priority date	Jun 29, 2019
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

First claim

What is claimed is:

1. A hardware processor comprising:
an address generation unit to generate a linear address for a memory access request to a memory;
at least one control register comprising a masking bit; and
a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the masking bit to produce a resultant linear address, and output the resultant linear address,
wherein one of:
the masking bit comprises a supervisor mode masking bit, and the memory management unit is to mask out the proper subset of bits inside the address space of the linear address for the memory access request by an operating system kernel when the supervisor mode masking bit is set,
the masking bit comprises a user mode masking bit, and the memory management unit is to mask out the proper subset of bits inside the address space of the linear address for the memory access request by a user application when the user mode masking bit is set, or
the masking bit comprises the supervisor mode masking bit and the user mode masking bit, and the memory management unit is to not mask out the proper subset of bits inside the address space of the linear address for the memory access request by the operating system kernel to a user pointer when the supervisor mode masking bit is not set and the user mode masking bit is set.

2. The hardware processor of claim 1 , wherein the proper subset of bits does not include a trailing bit of the linear address and does not include a leading bit of the linear address.

3. The hardware processor of claim 1 , wherein the proper subset of bits of the linear address comprises metadata that is masked out in the resultant linear address by the memory management unit.

4. The hardware processor of claim 1 , wherein the one is the masking bit comprises the supervisor mode masking bit, and the memory management unit is to mask out the proper subset of bits inside the address space of the linear address for the memory access request by the operating system kernel when the supervisor mode masking bit is set.

5. The hardware processor of claim 1 , wherein the one is the masking bit comprises the user mode masking bit, and the memory management unit is to mask out the proper subset of bits inside the address space of the linear address for the memory access request by the user application when the user mode masking bit is set.

6. The hardware processor of claim 1 , wherein the one is the masking bit comprises the supervisor mode masking bit and the user mode masking bit, and the memory management unit is to not mask out the proper subset of bits inside the address space of the linear address for the memory access request by the operating system kernel to the user pointer when the supervisor mode masking bit is not set and the user mode masking bit is set.

7. The hardware processor of claim 6 , wherein all pages corresponding to non-masked linear addresses of the proper subset of bits inside the address space are aliased to a same page as used for a masked linear address of the proper subset of bits.

8. The hardware processor of claim 6 , wherein the mask out of the proper subset of bits is zeroing the proper subset of bits.

9. A method comprising:
generating a linear address for a memory access request to a memory with an address generation unit of a hardware processor;
populating at least one control register comprising a masking bit of the hardware processor;
masking out a proper subset of bits inside an address space of the linear address for the memory access request by a memory management unit coupled to the hardware processor based on the masking bit to produce a resultant linear address; and
outputting the resultant linear address,
wherein one of:
the masking bit comprises a supervisor mode masking bit, and the masking comprises masking out the proper subset of bits inside the address space of the linear address for the memory access request by an operating system kernel when the supervisor mode masking bit is set,
the masking bit comprises a user mode masking bit, and the masking comprises masking out the proper subset of bits inside the address space of the linear address for the memory access request by a user application when the user mode masking bit is set, or
the masking bit comprises the supervisor mode masking bit and the user mode masking bit, and the masking does not mask out the proper subset of bits inside the address space of the linear address for the memory access request by the operating system kernel to a user pointer when the supervisor mode masking bit is not set and the user mode masking bit is set.

10. The method of claim 9 , wherein the proper subset of bits does not include a trailing bit of the linear address and does not include a leading bit of the linear address.

11. The method of claim 9 , wherein the proper subset of bits of the linear address comprises metadata that is masked out in the resultant linear address by the memory management unit.

12. The method of claim 9 , wherein the one is the masking bit comprises the supervisor mode masking bit, and the masking comprises masking out the proper subset of bits inside the address space of the linear address for the memory access request by the operating system kernel when the supervisor mode masking bit is set.

13. The method of claim 9 , wherein the one is the masking bit comprises the user mode masking bit, and the masking comprises masking out the proper subset of bits inside the address space of the linear address for the memory access request by the user application when the user mode masking bit is set.

14. The method of claim 9 , wherein the one is the masking bit comprises the supervisor mode masking bit and the user mode masking bit, and the masking does not mask out the proper subset of bits inside the address space of the linear address for the memory access request by the operating system kernel to the user pointer when the supervisor mode masking bit is not set and the user mode masking bit is set.

15. The method of claim 14 , further comprising aliasing all pages corresponding to non-masked linear addresses of the proper subset of bits inside the address space to a same page as used for a masked linear address of the proper subset of bits.

16. The method of claim 14 , wherein the masking out of the proper subset of bits is zeroing the proper subset of bits.

17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
generating a linear address for a memory access request to a memory with an address generation unit of a hardware processor;
populating at least one control register comprising a masking bit of the hardware processor;
masking out a proper subset of bits inside an address space of the linear address for the memory access request by a memory management unit coupled to the hardware processor based on the masking bit to produce a resultant linear address; and
outputting the resultant linear address,
wherein one of:
the masking bit comprises a supervisor mode masking bit, and the masking comprises masking out the proper subset of bits inside the address space of the linear address for the memory access request by an operating system kernel when the supervisor mode masking bit is set,
the masking bit comprises a user mode masking bit, and the masking comprises masking out the proper subset of bits inside the address space of the linear address for the memory access request by a user application when the use

Assignees

• Intel Corp

Inventors

• Gabor Ron
• Yanover Igor

Classifications

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F11/004 Primary

  Error avoidance (G06F11/07 and subgroups take precedence) · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title