Apparatus and method for power virus protection in a processor

Patent metadata

Field	Value
Publication number	US-11809549-B2
Application number	US-201916728843-A
Country	US
Kind code	B2
Filing date	Dec 27, 2019
Priority date	Dec 27, 2019
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

First claim

What is claimed is:

1. A processor comprising:
first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction;
detection circuitry to detect one or more instructions of a particular type and/or width;
evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry on performance of the processor to determine whether to enable the PVP circuitry, wherein upon being enabled, the PVP circuitry is to determine whether to trigger one or more throttling operations when executing the one or more instructions based on the detected instruction types and/or widths; and
control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

2. The processor of claim 1 wherein the evaluation circuitry is to compare one or more variables related to execution of the one or more instructions with and without the PVP circuitry being enabled.

3. The processor of claim 2 wherein responsive to the evaluation performed by the evaluation circuitry, the control circuitry is to disable the PVP circuitry or modify a configuration of the PVP circuitry.

4. The processor of claim 1 wherein the evaluation circuitry is to assign weights to the one or more instructions and to use the weights to perform the evaluation.

5. The processor of claim 3 wherein instructions having different widths are to be assigned different weights.

6. The processor of claim 1 further comprising:
execution circuitry to execute the one or more instructions, and
wherein the PVP circuitry is to apply power virus protection during the execution in accordance with the configuration performed by the control circuitry.

7. The processor of claim 6 further comprising:
a plurality of cores to process a plurality of threads, a first core to include the instruction fetch circuitry and the execution circuitry; and
a power manager comprising the evaluation circuitry to evaluate the impact of the PVP circuitry based on data received from the plurality of cores to generate a PVP configuration result, the power manager to transmit the PVP configuration result to the plurality of cores over an interconnect.

8. The processor of claim 7 wherein each core of the plurality of cores comprises at least a portion of the control circuitry to configure the PVP circuitry based on the PVP configuration result.

9. The processor of claim 8 wherein the data received from the plurality of cores comprises PVP threshold and/or throttling parameters and wherein the evaluation circuitry is to generate the PVP configuration result in accordance with a specified maximum current value.

10. The processor of claim 7 wherein detection circuitry of each core of the plurality of cores comprises:
sliding window energy cost circuitry/logic to determine at least one energy cost value associated with a specified periodic time window; and
a threshold comparator to determine whether an energy cost value is beyond a specified threshold and, if so, to transmit an indication of the energy cost value being beyond the threshold to the power manager.

11. A method comprising:
fetching instructions in a processor, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction;
detecting one or more instructions of a particular type and/or width;
evaluating, by evaluation circuitry, an impact of power virus protection (PVP) on performance of the processor to determine whether to enable the PVP by PVP circuitry, wherein upon being enabled, the PVP circuitry is to determine whether to trigger one or more throttling operations when executing the one or more instructions based on the detected instruction types and/or widths; and
configuring the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

12. The method of claim 11 wherein evaluating comprises comparing one or more variables related to execution of the one or more instructions with and without the PVP circuitry being enabled.

13. The method of claim 12 wherein configuring comprises disabling the PVP circuitry or modifying a configuration of the PVP circuitry.

14. The method of claim 11 wherein evaluating comprises assigning weights to the one or more instructions and using the weights to perform the evaluation.

15. The method of claim 13 wherein instructions having different widths are to be assigned different weights.

16. The method of claim 11 further comprising:
executing the one or more instructions, and
applying power virus protection during the execution in accordance with configuring the PVP circuitry.

17. The method of claim 16 wherein the operations of fetching and executing are performed on a first core of a plurality of cores, the method further comprising:
processing a plurality of threads on the plurality of cores, wherein the evaluating is performed on a power manager to evaluate the impact of the PVP circuitry based on data received from the plurality of cores to generate a PVP configuration result, the power manager to transmit the PVP configuration result to the plurality of cores over an interconnect.

18. The method of claim 17 wherein each core of the plurality of cores comprises at least a portion of the configuring of the PVP circuitry based on the PVP configuration result.

19. The method of claim 18 wherein the data received from the plurality of cores comprises PVP threshold and/or throttling parameters and wherein the evaluation circuitry is to generate the PVP configuration result in accordance with a specified maximum current value.

20. The method of claim 17 wherein detecting further comprises:
determining at least one energy cost value associated with a specified periodic time window; and
determining that an energy cost value is beyond a specified threshold; and
transmitting an indication of the energy cost value being beyond the threshold to the power manager.

Assignees

• Intel Corp

Inventors

• Gendler Alexander
• Meller Sagi
• Berger Gavri
• Yanover Igor

Classifications

• G06F21/54 Primary

  by adding security routines or objects to programs · CPC title

• G06F1/32

  Means for saving power · CPC title

• G06F9/3802

  Instruction prefetching · CPC title

• G06F21/561

  Virus type analysis · CPC title

• G06F2221/034

  Test or assess a computer or a system · CPC title