Multichip packages with 3D integration
US-12588557-B2 · Mar 24, 2026 · US
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Van Gemert Leo patents
Van Gemert Leo is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Van Gemert Leo |
| Total patents | 27 |
| First publication | May 25, 2017 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Double-sided multichip packages
US-12538844-B2 · Jan 27, 2026 · US
System
US-12476355-B2 · Nov 18, 2025 · US
Selective underfill assembly and method therefor
US-12183595-B2 · Dec 31, 2024 · US
Multichip packages with 3d integration
US-2024186303-A1 · Jun 6, 2024 · US
Double-sided multichip packages
US-2024186301-A1 · Jun 6, 2024 · US
System
US-2024154300-A1 · May 9, 2024 · US
Efficient wave guide transition between package and PCB using solder wall
US-11963291-B2 · Apr 16, 2024 · US
Semiconductor device with through package via and method therefor
US-2024088068-A1 · Mar 14, 2024 · US
Semiconductor device with under-bump metallization and method therefor
US-2024014152-A1 · Jan 11, 2024 · US
Recent patents
Latest publications not already listed above.
Efficient Wave Guide Transition Between Package and PCB Using Solder Wall
US-2023345623-A1 · Oct 26, 2023 · US
Selective underfill assembly and method therefor
US-2023108902-A1 · Apr 6, 2023 · US
Selective underfill assembly and method therefor
US-11557491-B2 · Jan 17, 2023 · US
Method and apparatus for improved circuit structure thermal reliability on printed circuit board materials
US-11508669-B2 · Nov 22, 2022 · US
Semiconductor device and method of making a semiconductor device
US-11011446-B2 · May 18, 2021 · US
Selective underfill assembly and method therefor
US-2021134612-A1 · May 6, 2021 · US
Method and Apparatus for improved Circuit Structure Thermal Reliability on Printed Circuit Board Materials
US-2021066209-A1 · Mar 4, 2021 · US
Underbump metallization dimension variation with improved reliability
US-10825789-B1 · Nov 3, 2020 · US
Apparatus comprising a semiconductor arrangement
US-10613136-B2 · Apr 7, 2020 · US
Integrated circuit package
US-10615134-B2 · Apr 7, 2020 · US
Component carrier
US-10315821-B2 · Jun 11, 2019 · US
Apparatus comprising a semiconductor arrangement
US-2019011496-A1 · Jan 10, 2019 · US
Wafer level chip scale semiconductor package
US-10109564-B2 · Oct 23, 2018 · US
Integrated circuit package
US-2018233465-A1 · Aug 16, 2018 · US
Component carrier
US-2018134473-A1 · May 17, 2018 · US
Wafer level chip scale semiconductor package
US-2017372988-A1 · Dec 28, 2017 · US
Semiconductor device and method of making a semiconductor device
US-2017148697-A1 · May 25, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Nxp Bv | 20 |
| Nxp Usa Inc | 5 |
| Nxp Bv | 1 |
| Nexperia BV | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/724 | 15 |
| H01L24/16 | 14 |
| H10W70/65 | 13 |
| H10W72/20 | 12 |
| H01L23/66 | 11 |