Apparatus comprising a semiconductor arrangement

Patent metadata

Field	Value
Publication number	US-10613136-B2
Application number	US-201816030006-A
Country	US
Kind code	B2
Filing date	Jul 9, 2018
Priority date	Jul 7, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.

First claim

The invention claimed is:

1. An apparatus comprising:
a substrate;
an integrated circuit region formed in the substrate;
a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and
a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate; and
an internal defect sensor comprising a conductive track, the conductive track of the internal defect sensor is disposed inwardly of the seal ring and arranged to at least partially surround the integrated circuit, wherein the defect sensor and the internal defect sensor are coupled to a defect detection circuit via a switch.

2. The apparatus of claim 1 , wherein the integrated circuit region includes a defect detection circuitry within the seal ring for providing the detection signal between the first end terminal and the second end terminal.

3. The apparatus of claim 2 , wherein the connection between the defect detection circuitry and the first end terminal and the second end terminal is provided by a redistribution layer.

4. The apparatus of claim 3 , wherein the redistribution layer comprises a layer provided on the substrate and having an arrangement of metal to:
bridge the seal ring and connect the first end terminal and the second end terminal to the defect detection circuit; and
provide for connection of an input-output pad of the integrated circuit region to a bump pad, the bump pad and redistribution layer providing for connection of the input-output pad and therefore circuitry of the integrated circuit region to circuitry external to the apparatus.

5. The apparatus of claim 2 , wherein the defect sensor comprises a first defect sensor and the apparatus includes a second defect sensor, the second defect sensor comprising a second conductive track formed of at least one conductive layer in the substrate, the second conductive track disposed inwardly of the seal ring and arranged to at least partially surround a periphery of the integrated circuit region, the second conductive track having a second-track-first-end terminal and a second-track-second-end terminal to provide for passing of a detection signal through the second conductive track to detect a break in the second conductive track and thereby a defect in the substrate.

6. The apparatus of claim 5 , wherein the defect detection circuitry includes a switch arrangement to switch between providing the detection signal to the first defect sensor and providing the detection signal to the second defect sensor.

7. The apparatus of claim 1 , wherein the substrate comprises a wafer and a plurality of semiconductor arrangements each comprising at least the integrated circuit region, the seal ring and the defect sensor, are provided on said wafer for dicing into individual semiconductor arrangements.

8. The apparatus of claim 7 , wherein the semiconductor arrangements comprise a wafer level chip scale packages.

9. The apparatus of claim 1 , in which the conductive track of the defect sensor comprises a plurality of metal layers arranged in different planes in the substrate, at least two of the metal layers connected to one another by a via.

10. A method of manufacturing an apparatus comprising:
providing, on a substrate having an integrated circuit region formed therein and a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture and ion ingress to the integrated circuit region, a defect sensor comprising a conductive track formed in at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to provide for passing of a detection signal through the conductive track to detect a break in the conductive track and thereby a defect in the substrate; and
providing an internal defect sensor comprising a conductive track, the conductive track of the internal defect sensor is disposed inwardly of the seal ring and arranged to at least partially surround the integrated circuit, wherein the defect sensor and the internal defect sensor are coupled to a defect detection circuit via a switch.

11. The method of claim 10 , wherein the integrated circuit region includes a defect detection circuitry within the seal ring for providing the detection signal between the first end terminal and the second end terminal, the method comprising:
providing a connection between the defect detection circuitry and the first end terminal and the second end terminal by provision of a redistribution layer.

12. The method of claim 11 , wherein the step of providing a connection comprises:
providing a redistribution layer on the substrate comprising an arrangement of metal to bridge and thereby extend over the seal ring and connect the first end terminal and the second end terminal to the defect detection circuit.

13. The method of claim 10 , wherein the substrate comprises a wafer and a plurality of semiconductor arrangements each comprising at least the integrated circuit region and the seal ring are provided on said wafer, the step of providing a defect sensor comprising providing a defect sensor for at least one of the semiconductor arrangements.

14. The method of claim 13 , wherein the method includes the step of dicing the wafer into individual semiconductor arrangements; and
providing for application of the detection signal to the defect sensor of the at least one semiconductor arrangements to detect any defects outwardly of the seal ring that cause a break in the conductive track.

15. A semiconductor manufacturing device configured to perform the method of claim 10 .

Assignees

• Nxp Bv

Inventors

• Van Gemert Leo
• Drummen Peter

Classifications

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• H01L21/78

  Electricity · mapped topic

• H01L24/05

  Electricity · mapped topic

• H01L23/585

  Electricity · mapped topic