Wafer level package without sidewall cracking

Patent metadata

Field	Value
Publication number	US-9318405-B2
Application number	US-201514702276-A
Country	US
Kind code	B2
Filing date	May 1, 2015
Priority date	May 1, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer. The molding compound may eliminate sidewall chipping and cracking as well as reduce the need for back side lamination.

First claim

What is claimed is:

1. A wafer level package device comprising:
a substrate including a non-active substrate side that extends between a first substrate sidewall and a second substrate sidewall and an active substrate side that extends between a third substrate sidewall and a fourth substrate sidewall, the first substrate sidewall opposite the second substrate sidewall and the third substrate sidewall opposite the fourth substrate sidewall;
an integrated circuit layer proximate the active substrate side;
a redistribution layer coupled to the integrated circuit layer, the redistribution layer including a metal layer and a dielectric layer; and
a molding compound including a first molding compound sidewall and a second molding compound sidewall opposite the first molding compound sidewall, the molding compound encapsulates the substrate and the integrated circuit layer such that a first width between the first molding compound sidewall and the first substrate sidewall is greater than a second width between the first molding compound sidewall and the third substrate sidewall, and the metal layer being free of the molding compound.

2. The wafer level package device of claim 1 , wherein the redistribution layer is configured to redistribute power to a plurality of active circuits of the integrated circuit layer.

3. The wafer level package device of claim 2 , wherein the molding compound is at least partially in contact with the dielectric layer.

4. The wafer level package device of claim 3 , wherein the dielectric layer is a photodielectric.

5. The wafer level package device of claim 1 , wherein the wafer level package device is incorporated into a device selected from a group comprising of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle, and further including the device.

6. A wafer level package device comprising:
a substrate including a non-active substrate side that extends between a first substrate sidewall and a second substrate sidewall and an active substrate side that extends between a third substrate sidewall and a fourth substrate sidewall, the first substrate sidewall opposite the second substrate sidewall and the third substrate sidewall opposite the fourth substrate sidewall;
an integrated circuit layer proximate the active substrate side;
a redistribution layer coupled to the integrated circuit layer, the redistribution layer including a metal layer and a dielectric layer; and
a molding compound including a first molding compound sidewall and a second molding compound sidewall opposite the first molding compound sidewall, the molding compound encapsulates the substrate and the integrated circuit layer while leaving the metal layer exposed such that a first width between the first molding compound sidewall and the first substrate sidewall is greater than a second width between the first molding compound sidewall and the third substrate sidewall.

7. The wafer level package device of claim 6 , wherein a third width between the second molding compound sidewall and the fourth substrate sidewall is approximately the second width between the first molding compound sidewall and the third substrate sidewall.

8. The wafer level package device of claim 7 , wherein the second width between the first molding compound sidewall and the third substrate sidewall is less than 10% of a fourth width of the substrate between the third substrate sidewall and the fourth substrate sidewall.

9. The wafer level package device of claim 8 , wherein a fifth width between the second molding compound sidewall and the second substrate sidewall is approximately the first width between the first molding compound sidewall and the first substrate sidewall.

10. The wafer level package device of claim 9 , wherein the redistribution layer is configured to redistribute power to a plurality of active circuits of the integrated circuit layer.

11. The wafer level package device of claim 10 , wherein the molding compound is at least partially in contact with the dielectric layer.

12. The wafer level package device of claim 11 , wherein the dielectric layer is a photodielectric.

13. The wafer level package device of claim 12 , further comprising a solder ball mounted on the dielectric layer and in contact with the metal layer.

14. A wafer level package device comprising:
a substrate including a non-active substrate side that extends between a first substrate sidewall and a second substrate sidewall and an active substrate side that extends between a third substrate sidewall and a fourth substrate sidewall, the first substrate sidewall opposite the second substrate sidewall and the third substrate sidewall opposite the fourth substrate sidewall;
an integrated circuit layer proximate the active substrate side;
a redistribution layer coupled to the integrated circuit layer, the redistribution layer including a dielectric layer in contact with the integrated circuit layer, a polymer layer on the dielectric layer, and a metal layer in the polymer layer;
a molding compound including a first molding compound sidewall even with the third substrate sidewall, a second molding compound sidewall even with the fourth substrate sidewall, a third molding compound sidewall that extends horizontally beyond the first molding compound sidewall, and a fourth molding compound sidewall that extends horizontally beyond the second molding compound sidewall; and
the molding compound encapsulates the substrate such that a sixth width between the third molding compound sidewall and the first substrate sidewall is greater than a first width between the first molding compound sidewall and the first substrate sidewall.

15. The wafer level package device of claim 14 , wherein an eighth width of the third molding compound sidewall extends horizontally beyond the first molding compound sidewall is less than 10% of a fourth width of the substrate between the third substrate sidewall and the fourth substrate sidewall, and a seventh width of the fourth molding compound sidewall extends horizontally beyond the second molding compound sidewall is approximately the eighth width between the third molding compound sidewall extends horizontally beyond the first molding compound sidewall.

16. The wafer level package device of claim 15 , wherein the first width between the first molding compound sidewall and the first substrate sidewall is smaller than the sixth width between the third molding compound sidewall and the first substrate sidewall.

17. The wafer level package device of claim 16 , wherein a fifth width between the second molding compound sidewall and the second substrate sidewall is approximately the first width between the first molding compound sidewall and the first substrate sidewall.

18. The wafer level package device of claim 17 , wherein the redistribution layer is configured to redistribute power to a plurality of active circuits of the integrated circuit layer.

19. The wafer level package device of claim 18 , wherein the molding compound is at least partially in contact with the dielectric layer.

20. The wafer level package device of claim 19 , wherein the dielectric layer is a photodielectric.

Assignees

• Qualcomm Inc

Inventors

• Xu Jianwen
• Keser Lizabeth Ann
• Stone William
• Bezuk Steve Joseph
• Yu Nicholas Ka Ming

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title