Multiple register memory access instructions, processors, methods, and systems

Patent metadata

Field	Value
Publication number	US-10170165-B2
Application number	US-201715855626-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Jun 28, 2013
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

First claim

What is claimed is:

1. A system comprising:
a system memory; and
a processor coupled to the system memory, the processor comprising:
a cache to store a plurality of cache lines;
a plurality of general purpose registers;
a plurality of 128-bit packed data registers, including a first source 128-bit packed data register, and a second source 128-bit packed data register;
an instruction fetch unit to fetch instructions, including a store to memory instruction;
a decode unit to decode the store to memory instruction, the store to memory instruction having a first field to specify the first source 128-bit packed data register, having a second field to specify the second source 128-bit packed data register, and indicating a starting memory location in the system memory at which to store data; and
a memory access unit coupled to the decode unit, and coupled to the plurality of 128-bit packed data registers, the memory access unit to perform a store to memory operation, in response to the decoded store to memory instruction, the store to memory operation to:
store a first 128-bit data from the first source 128-bit packed data register to the system memory starting at the indicated starting memory location; and
store a second 128-bit data from the second source 128-bit packed data register to the system memory at a location adjacently after the first 128-bit data.

2. The system of claim 1 , further comprising a plurality of write mask registers to predicate result vector writes.

3. The system of claim 1 , wherein the processor further comprises a 16-wide vector processing unit to execute double-precision float instructions.

4. The system of claim 1 , wherein the cache is to store 512-bit cache lines.

5. The system of claim 1 , wherein the cache is to store 1024-bit cache lines.

6. The system of claim 1 , wherein the cache is to store cache lines that are a multiple of a width of the 128-bit packed data registers.

7. The system of claim 1 , wherein the processor further comprises:
a branch prediction unit; and
a translation lookaside buffer (TLB).

8. The system of claim 1 , wherein the processor is a reduced instruction set computing (RISC) processor.

9. The system of claim 1 , further comprising audio I/O coupled to the processor.

10. The system of claim 1 , further comprising a communication device coupled to the processor.

11. The system of claim 1 , further comprising an I/O device coupled to the processor.

12. The system of claim 1 , further comprising a mass storage device coupled to the processor.

13. The system of claim 12 , wherein the mass storage device comprises a disk drive.

14. The system of claim 1 , further comprising a Peripheral Component Interconnect (PCI) Express bus coupled to the processor.

15. The system of claim 1 , further comprising a graphics processor coupled to the processor.

16. The system of claim 1 , wherein the system memory comprises dynamic random access memory (DRAM).

17. A method performed by a system, the method comprising:
storing data in a system memory;
storing a plurality of cache lines in a cache of a processor of the system;
storing data in a plurality of general purpose registers of the processor;
storing a first 128-bit data in a first source 128-bit packed data register of the processor;
storing a second 128-bit data in a second source 128-bit packed data register of the processor;
fetching a store to memory instruction with an instruction fetch unit of the processor;
decoding the store to memory instruction with a decode unit of the processor, the store to memory instruction having a first field specifying the first source 128-bit packed data register, having a second field specifying the second source 128-bit packed data register, and indicating a starting memory location in a memory at which to store data; and
performing a store to memory operation, in response to the decoded store to memory instruction, the store to memory operation including:
storing the first 128-bit data from the first source 128-bit packed data register to the memory starting at the indicated starting memory location; and
storing the second 128-bit data from the second source 128-bit packed data register to the memory at a location adjacently after the first 128-bit data.

18. The method of claim 17 , further comprising transmitting data on a Peripheral Component Interconnect (PCI) Express bus coupled to the processor.

19. An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a set of instructions, including a store to memory instruction, the set of instructions if processed by a system to cause the system to perform operations comprising to:
store data in a system memory;
store a plurality of cache lines in a cache of a processor of the system;
store data in a plurality of general purpose registers of the processor;
store a first 128-bit data in a first source 128-bit packed data register of the processor; and
store a second 128-bit data in a second source 128-bit packed data register of the processor; and
the store to memory instruction if processed by the system to cause the system to perform operations comprising to:
decode the store to memory instruction with a decode unit of the processor, the store to memory instruction having a first field to specify the first source 128-bit packed data register, having a second field to specify the second source 128-bit packed data register, and to indicate a starting memory location in the memory at which to store data; and
perform a store to memory operation, in response to the decoded store to memory instruction, the store to memory operation to:
store the first 128-bit data from the first source 128-bit packed data register to the memory starting at the indicated starting memory location; and
store the second 128-bit data from the second source 128-bit packed data register to the memory at a location adjacently after the first 128-bit data.

20. The article of manufacture of claim 19 , wherein the set of instructions, if processed by the machine, are to cause the machine to perform operations comprising to transmit data on a Peripheral Component Interconnect (PCI) Express bus.

Assignees

• Intel Corp

Inventors

• Hinton Glenn
• Toll Bret
• Singhal Ronak

Classifications

• G11C7/1036 Primary

  using data shift registers · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title