De-prioritizing speculative code lines in on-chip caches

Patent metadata

Field	Value
Publication number	US-12417182-B2
Application number	US-202117551172-A
Country	US
Kind code	B2
Filing date	Dec 14, 2021
Priority date	Dec 14, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
logic circuitry to determine whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache; and
the logic circuitry to cause de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure,
wherein the code miss request is directed at the shared cache, wherein the storage structure is to store an indicia or a virtual address of one or more instructions or one or more micro-operations that have been allocated in an Instruction Dispatch Queue (IDQ), wherein the IDQ is to store an instruction or micro-operation prior to allocation in a pre-execution stage of a processor pipeline.

2. The apparatus of claim 1 , wherein the storage structure comprises a Bloom filter.

3. The apparatus of claim 1 , wherein the shared cache is a Level 2 (L2) cache.

4. The apparatus of claim 1 , wherein the code miss request is directed at the shared cache after a miss in a code Level 1 (L1) cache.

5. The apparatus of claim 1 , wherein the logic circuitry is to forward the code miss request to the shared cache with an indication to de-prioritize the code line in the shared cache in response to the absence of the reference in the storage structure.

6. The apparatus of claim 1 , wherein the shared cache is to be shared amongst a plurality of processor cores of a processor.

7. The apparatus of claim 1 , wherein a processor, having one or more processor cores, comprises one or more of: the logic circuitry and the shared cache.

8. An apparatus comprising:
a queue to store an entry for one or more recently fetched code lines from a shared cache; and
logic circuitry to determine whether the queue includes a matching entry corresponding to an instruction or micro-operation stored in an Instruction Dispatch Queue (IDQ); and
the logic circuitry to cause de-prioritization of a code line in the shared cache in response to an absence of the matching entry in the queue.

9. The apparatus of claim 8 , wherein each entry of the queue comprises a physical address of a code line, a virtual address of the code line, an IDQ write flag for the code line, and a valid flag for the code line.

10. The apparatus of claim 9 , wherein the IDQ write flag is to be updated in response to storage of the instruction or micro-operation in the IDQ.

11. The apparatus of claim 8 , wherein the logic circuitry is to cause transmission of a request to the shared cache to cause de-prioritization of the code line in the shared cache.

12. The apparatus of claim 11 , wherein the request comprises an address of the code line and an indication to de-prioritize the code line in the shared cache.

13. The apparatus of claim 8 , wherein the shared cache is a Level 2 (L2) cache.

14. The apparatus of claim 8 , wherein the shared cache is to be shared amongst a plurality of processor cores of a processor.

15. The apparatus of claim 8 , wherein a processor, having one or more processor cores, comprises one or more of: the logic circuitry and the shared cache.

16. One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform:
determining whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache; and
causing de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure,
wherein the code miss request is directed at the shared cache, and wherein the storage structure is to store an indicia or a virtual address of one or more instructions or one or more micro-operations that have been allocated in an Instruction Dispatch Queue (IDQ), wherein the IDQ is to store an instruction or micro-operation prior to allocation in a pre-execution stage of a processor pipeline.

17. The one or more computer-readable media of claim 16 , wherein the storage structure comprises a Bloom filter.

18. The one or more computer-readable media of claim 16 , wherein the shared cache is a Level 2 (L2) cache.

19. The one or more computer-readable media of claim 16 , wherein the code miss request is directed at the shared cache after a miss in a code Level 1 (L1) cache.

20. The one or more computer-readable media of claim 16 , further comprising one or more instructions that when executed on the processor configure the processor to perform forwarding the code miss request to the shared cache with an indication to de-prioritize the code line in the shared cache in response to the absence of the reference in the storage structure.

21. The one or more computer-readable media of claim 16 , further comprising one or more instructions that when executed on the processor configure the processor to perform sharing the shared cache amongst a plurality of processor cores of the processor.

Assignees

• Intel Corp

Inventors

• Nori Anant Vithal
• Kallurkar Prathmesh
• Soundararajan Niranjan Kumar
• Subramoney Sreenivas
• Rappoport Lihu
• Alam Hanna
• Moga Adrian
• Singhal Ronak

Classifications

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title