Allocation and synchronization of multiple queues by a graphics processing unit

Patent metadata

Field	Value
Publication number	US-2025265762-A1
Application number	US-202418444458-A
Country	US
Kind code	A1
Filing date	Feb 16, 2024
Priority date	Feb 16, 2024
Publication date	Aug 21, 2025
Grant date	—

Abstract

A system that includes a graphics processing unit (GPU) comprising multiple processors and circuitry to: parse a first queue of the multiple queues; at an arbitration point in the first queue, select a second queue of the multiple queues to parse based on a priority level of the second queue and a head of line blocking condition of the second queue; and based on identification of a thread spawning instruction, enqueue the thread spawning instruction for execution by at least one processor of the multiple processors.

First claim

1 . An apparatus comprising:
at least one memory to store multiple queues; and a graphics processing unit (GPU) comprising multiple processors and circuitry to:
parse a first queue of the multiple queues;
at an arbitration point in the first queue, select a second queue of the multiple queues to parse based on a priority level of the second queue and a head of line blocking condition of the second queue; and
based on identification of a thread spawning instruction, enqueue the thread spawning instruction for execution by at least one processor of the multiple processors.

2 . The apparatus of claim 1 , wherein the arbitration point comprises a memory polling command or pipeline flush command.

3 . The apparatus of claim 1 , wherein the GPU to select the second queue of the multiple queues to parse based on the priority level of the second queue and the head of line blocking condition of the second queue is to select the second queue over a third queue of the multiple queues based on the second queue having a higher priority level than the third queue and the third queue being subject to a head of line blocking condition.

4 . The apparatus of claim 1 , wherein the GPU to select the second queue of the multiple queues to parse based on the priority level of the second queue and the head of line blocking condition of the second queue is to select the second queue over a third queue of the multiple queues based on the second queue having a same priority level as the third queue and a round robin selection.

5 . The apparatus of claim 1 , wherein the head of line blocking condition comprises a memory polling command or pipeline flush command.

6 . The apparatus of claim 1 , wherein the circuitry is to cause execution of a same queue of the multiple queues by the multiple processors and prevent a first processor of the multiple processors from executing a different queue than a second processor of the multiple processors until all processors of a group have completed processing the same queue.

7 . The apparatus of claim 6 , wherein the at least one memory is to store a token indicative of a number of processors that have accessed a particular queue and wherein the circuitry is to cause execution of the same queue of the multiple queues by the processors of the group and prevent the first processor of the multiple processors from executing the different queue than the second processor of the multiple processors until all processors of the group have completed processing the same queue based on access to the token.

8 . A non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
configure a graphics processing unit (GPU) comprising multiple processors and circuitry to: at a head of line blocking event in a first queue of multiple queues, select a second queue of the multiple queues for processing based on a priority level of the second queue and no head of line blocking condition of the second queue; and based on identifying a thread spawning instruction, enqueue the thread spawning instruction for execution by at least one processor of the multiple processors of the GPU.

9 . The computer-readable medium of claim 8 , wherein the head of line blocking event comprises a memory polling command or pipeline flush command.

10 . The computer-readable medium of claim 8 , wherein the GPU to select the second queue of the multiple queues for processing based on the priority level of the second queue and no head of line blocking condition of the second queue is to select the second queue over a third queue of the multiple queues based on the second queue having a higher priority level than the third queue and the third queue being subject to a head of line blocking condition.

11 . The computer-readable medium of claim 8 , wherein the GPU to select the second queue of the multiple queues for processing based on the priority level of the second queue and no head of line blocking condition of the second queue is to select the second queue over a third queue of the multiple queues based on the second queue having a same priority level as the third queue and a round robin selection.

12 . The computer-readable medium of claim 8 , wherein the GPU to select the second queue of the multiple queues for processing based on the priority level of the second queue and no head of line blocking condition of the second queue is to select the second queue over a third queue of the multiple queues based on the second queue having a largest number of unexecuted instructions among the multiple queues.

13 . The computer-readable medium of claim 8 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
cause processing of a same queue of the multiple queues by the multiple processors and prevent a first processor of the multiple processors from executing a different queue than a second processor of the multiple processors until all processors of a group have completed processing the same queue.

14 . The computer-readable medium of claim 13 , wherein the cause processing of the same queue of the multiple queues by the multiple processors and prevent the first processor of the multiple processors from executing the different queue than the second processor of the multiple processors until all processors of the group have completed processing the same queue is based on a token indicative of a number of processors that have accessed a particular queue.

15 . A method comprising:
a command streamer of a graphics processing unit (GPU), comprising multiple processors, performing:
at a head of line blocking event in a first queue of multiple queues, selecting a second queue of the multiple queues for processing based on a priority level of the second queue and no head of line blocking condition of the second queue; and
based on identifying a thread spawning instruction, enqueueing the thread spawning instruction for execution by at least one processor of the multiple processors of the GPU.

16 . The method of claim 15 , wherein the head of line blocking event comprises a memory polling command or pipeline flush command.

17 . The method of claim 15 , wherein the selecting the second queue of the multiple queues for processing based on the priority level of the second queue and no head of line blocking condition of the second queue comprises:
selecting the second queue over a third queue of the multiple queues based on the second queue having a higher priority level than the third queue and the third queue being subject to a head of line blocking condition.

18 . The method of claim 15 , wherein the selecting the second queue of the multiple queues for processing based on the priority level of the second queue and no head of line blocking condition of the second queue comprises:
selecting the second queue over a third queue of the multiple queues based on the second queue having a same priority level as the third queue and a round robin selection.

19 . The method of claim 15 , wherein the selecting the second queue of the multiple queues for processing based on the priority level of the second queue and no head of line blocking condition of the second queue comprises:
selecting the second queue over a third queue of the multiple queues based on the second queue having a largest number of unexecuted instructions among the multiple queues.

20 . The method of claim 15 , comprisi

Assignees

• Intel Corp

Inventors

• Mrozek Michal
• Boudier Pierre
• Boles Jeffery S
• Aman
• Ranganathan Vasanth
• Navale Aditya
• Damon William
• David Rebecca
• Nalluri Hema C
• Valles Antonio

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title