Graphics processor mid-thread preemption

Patent metadata

Field	Value
Publication number	US-2025232511-A1
Application number	US-202418414807-A
Country	US
Kind code	A1
Filing date	Jan 17, 2024
Priority date	Jan 17, 2024
Publication date	Jul 17, 2025
Grant date	—

Abstract

Techniques are provided to enable mid-thread (instruction level) preemption in a graphics processor without requiring software intervention by a graphics driver associated with the graphics processor. Hardware based mid-thread preemption is facilitated using the thread dispatch hardware of the graphics processor to trigger execution of a kernel program by the graphics processor that saves the thread state of preempted processing resources and facilitates the subsequent restoration of that thread state to the same or a different set of processing resources.

First claim

What is claimed is:

1 . A graphics processor comprising:
a memory interface; a plurality of graphics cores coupled via a data interconnect, each graphics core of the plurality of graphics cores including a plurality of processing resources; and circuitry to manage execution of workloads by the plurality of graphics cores, the circuitry configured to:
dispatch a first plurality of threads on behalf of a first thread group to be executed by a first set of processing resources of the plurality of processing resources;
receive a command to perform mid-thread preemption of the first thread group;
trigger, on the first set of processing resources, execution of a kernel program to save execution state for the first set of processing resources to memory of the graphics processor; and
replace the first thread group on the first set of processing resources of with a second thread group after the execution state for the first set of processing resources is saved.

2 . The graphics processor of claim 1 , wherein the plurality of graphics cores is arranged in a plurality of slices, each slice has a plurality of subslices including a plurality of processing resources, each subslice is independently preemptable, and the first set of processing resources is associated with a first subslice.

3 . The graphics processor of claim 2 , wherein the circuitry is configured to replace the first thread group on the first subslice concurrently with execution of a third thread group via a second subslice.

4 . The graphics processor of claim 3 , wherein the circuitry is to trigger the execution of the kernel program to save the execution state for the first set of processing resources via an interrupt routine triggered for execution on each processing resource of the first subslice.

5 . The graphics processor of claim 4 , wherein the interrupt routine is to cause execution of the kernel program, the kernel program to save the execution state for the first set of processing resources to a thread state buffer within the memory of the graphics processor.

6 . The graphics processor of claim 5 , wherein each subslice is to be respectively associated with a separate thread state buffer.

7 . The graphics processor of claim 5 , wherein the execution state for the first set of processing resources includes an active thread state of the first subslice upon receipt of the command to perform the mid-thread preemption, the active thread state including general-purpose registers, architecture specific registers, shared local memory, and barrier state.

8 . The graphics processor of claim 1 , the circuitry configured to:
receive a command to trigger a restore event for the first thread group; in response to the command to trigger the restore event, dispatch a third plurality of threads to a second set of processing resources of the graphics processor, the third plurality of threads to restore the execution state saved for the first set of processing resources to the second set of processing resources; and resume execution of the first thread group at the second set of processing resources via the third plurality of threads.

9 . The graphics processor of claim 8 , wherein the second set of processing resources differs from the first set of processing resources.

10 . The graphics processor of claim 9 , wherein the first set of processing resources are configured, via kernel program code, to construct a restore batch buffer to cause restoration of the execution state, the restore batch buffer to be executed in response to the command to trigger the restore event.

11 . A method for performing mid-thread preemption in a graphics processor configured to execute compute programs, the method comprising:
dispatching a first plurality of threads to a first plurality of processing resources of the graphics processor on behalf of a first thread group to be executed by the first plurality of processing resources; receiving a command to perform mid-thread preemption of the first thread group; executing, on the first plurality of processing resources, a kernel program to save execution state for the first plurality of processing resources to memory of the graphics processor; and replacing the first thread group on the first plurality of processing resources with a second thread group after the execution state for the first plurality of processing resources is saved.

12 . The method of claim 11 , wherein the graphics processor includes a plurality of graphics cores is arranged in a plurality of slices, each slice having a plurality of subslices including a plurality of processing resources, each subslice is independently preemptable, and the first plurality of processing resources is associated with a first subslice.

13 . The method of claim 12 , further comprising replacing the first thread group on the first subslice concurrently with execution of a third thread group via a second subslice.

14 . The method of claim 11 , further comprising:
receiving a command to restore the first thread group; dispatching a third plurality of threads to a second plurality of processing resources of the graphics processor; and restoring, via the third plurality of threads, the execution state saved for the first plurality of processing resources to the second plurality of processing resources.

15 . The method of claim 14 , wherein executing, on the first plurality of processing resources, the kernel program to save the execution state for the first plurality of processing resources includes interrupting program code associated with the first thread group and executing the kernel program at each of the first plurality of processing resources.

16 . The method of claim 15 , further building a restore command buffer via the kernel program in association with saving the execution state for the first plurality of processing resources, wherein executing the restore command buffer causes restoration of the execution state of the first thread group to the second plurality of processing resources.

17 . The method of claim 16 , further comprising resuming execution of the first thread group at the second plurality of processing resources, wherein the second plurality of processing resources differ from the first plurality of processing resources and has a different number of processing resources than the first plurality of processing resources.

18 . A graphics processing system comprising:
a memory device; and a graphics processor comprising a memory interface coupled with the memory device, the graphics processor including a plurality of graphics cores coupled via a data interconnect, each graphics core of the plurality of graphics cores including a plurality of processing resources, and circuitry to manage execution of workloads by the plurality of graphics cores, the circuitry configured to:
dispatch a first plurality of threads on behalf of a first thread group to be executed by a first set of processing resources of the plurality of processing resources;
receive a command to perform mid-thread preemption of the first thread group;
trigger, on the first set of processing resources, execution of a kernel program to save execution state for the first set of processing resources to memory of the graphics processor; and
replace the first thread group on the first set of processing resources of with a second thread group after the execution state for the first set of processing resources is saved.

19 . The graphics processing system of claim 18 , wherein the plural

Assignees

• Intel Corp

Inventors

• Ranganathan Vasanth
• Valerio James
• Navale Aditya
• Curtis Alan
• Boles Jeffery S
• Nalluri Hema Chand
• Vemulapalli Vikranth
• Pal Supratim
• Kuznetsov Boris
• Schwartz Brent A

Classifications

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06T15/503

  Blending, e.g. for anti-aliasing · CPC title

• G06T15/205

  Image-based rendering · CPC title