Dynamic precision for neural network compute operations

Patent metadata

Field	Value
Publication number	US-12346798-B2
Application number	US-202318351124-A
Country	US
Kind code	B2
Filing date	Jul 12, 2023
Priority date	Apr 24, 2017
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
processor circuitry coupled to a memory, the processor circuitry to:
track precision level data relating to one or more neural network operations; and
expose the precision level data in one or more model specific registers, wherein the one or more model specific registers are used to tune one or more neural network applications executing on the processor circuitry.

2. The apparatus of claim 1 , wherein tracking further includes tracking one or more weights associated with the one or more neural network operations, wherein tracking is performed while a neural network application is being executed on the processor circuitry.

3. The apparatus of claim 1 , wherein the processor circuitry is further to automatically schedule, based on the precision level data, runtimes for workloads associated with the processor circuitry.

4. The apparatus of claim 1 , wherein the processor circuitry comprises one or more of graphics processor circuitry or application processor circuitry.

5. A method comprising:
tracking, by a processor of a computing device, precision level data relating to one or more neural network operations; and
exposing the precision level data in one or more model specific registers, wherein the one or more model specific registers are used to tune one or more neural network applications executing on the processor.

6. The method of claim 5 , wherein tracking further includes tracking one or more weights associated with the one or more neural network operations, wherein tracking is performed while a neural network application is being executed on the processor.

7. The method of claim 5 , further comprising automatically scheduling, based on the precision level data, runtimes for workloads associated with the processor.

8. The method of claim 5 , wherein the processor comprises a graphics processor coupled to a memory and an application processor.

9. At least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
tracking precision level data relating to one or more neural network operations; and
exposing the precision level data in one or more model specific registers, wherein the one or more model specific registers are used to tune one or more neural network applications executing on the one or more processors.

10. The non-transitory computer-readable medium of claim 9 , wherein tracking further includes tracking one or more weights associated with the one or more neural network operations, wherein tracking is performed while a neural network application is being executed on one or more processors of the computing device.

11. The non-transitory computer-readable medium of claim 9 , wherein the operations further comprise automatically scheduling, based on the precision level data, runtimes for workloads associated with one or more processors.

12. The non-transitory computer-readable medium of claim 9 , wherein the one or more processors comprise one or more graphics processors or one or more application processors.

Assignees

• Intel Corp

Inventors

• Sinha Kamal
• Vembu Balaji
• Nurvitadhi Eriko
• Galoppo Von Borries Nicolas C
• Barik Rajkishore
• Lin Tsung-Han
• Ray Joydeep
• Tang Ping T
• Strickland Michael S
• Chen Xiaoming
• Yao Anbang
• Shpeisman Tatiana
• Appu Abhishek R
• Koker Altug
• Akhbari Farshad
• Srinivasa Narayan
• Chen Feng
• Kim Dukhwan
• Satish Nadathur Rajagopalan
• Weast John C
• Macpherson Mike B
• Hurd Linda L
• Ranganathan Vasanth
• Jahagirdar Sanjeev

Classifications

• G06N3/08

  Learning methods · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/0895

  Weakly supervised learning, e.g. semi-supervised or self-supervised learning · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title