Flash memory having improved performance as a consequence of program direction along a flash storage cell column
US-2025364059-A1 · Nov 27, 2025 · US
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Ramanan Narayanan patents
Ramanan Narayanan is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ramanan Narayanan |
| Total patents | 21 |
| First publication | Oct 29, 2020 |
| Latest publication | Nov 27, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory cell sensing circuit with adjusted bias from pre-boost operation
US-12394492-B2 · Aug 19, 2025 · US
Program verify process having placement aware pre-program verify (PPV) bucket size modulation
US-12322455-B2 · Jun 3, 2025 · US
NAND sensing circuit and technique for read-disturb mitigation
US-12266406-B2 · Apr 1, 2025 · US
Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit
US-12237023-B2 · Feb 25, 2025 · US
Modulation of source voltage in nand-flash array read
US-2024363173-A1 · Oct 31, 2024 · US
Modulation of source voltage in NAND-flash array read
US-12087365-B2 · Sep 10, 2024 · US
Method and apparatus to mitigate hot electron read disturbs in 3D nand devices
US-12051469-B2 · Jul 30, 2024 · US
Program verify process having placement aware pre-program verify (ppv) bucket size modulation
US-2022366991-A1 · Nov 17, 2022 · US
Nand sensing circuit and technique for read-disturb mitigation
US-2022293193-A1 · Sep 15, 2022 · US
Recent patents
Latest publications not already listed above.
Modulation of source voltage in nand-flash array read
US-2022293194-A1 · Sep 15, 2022 · US
Method and apparatus to mitigate hot electron read disturbs in 3d nand devices
US-2022284968-A1 · Sep 8, 2022 · US
Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit
US-2022208286-A1 · Jun 30, 2022 · US
Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices
US-11355199-B2 · Jun 7, 2022 · US
Memory cell sensing circuit with adjusted bias from pre-boost operation
US-2022172784-A1 · Jun 2, 2022 · US
Flash memory having improved performance as a consequence of program direction along a flash storage cell column
US-2022084606-A1 · Mar 17, 2022 · US
Method and apparatus to mitigate hot electron read disturbs in 3d nand devices
US-2022028459-A1 · Jan 27, 2022 · US
Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell
US-2021257036-A1 · Aug 19, 2021 · US
Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell
US-11094386-B1 · Aug 17, 2021 · US
Program verify technique for non-volatile memory
US-10847234-B2 · Nov 24, 2020 · US
Program verify technique for non-volatile memory
US-2020342946-A1 · Oct 29, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 15 |
| Intel NDTM US LLC | 8 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/26 | 19 |
| G11C16/0483 | 19 |
| G11C16/08 | 17 |
| G11C16/3427 | 13 |
| G11C11/5642 | 12 |