Method and apparatus to mitigate hot electron read disturbs in 3D nand devices

Patent metadata

Field	Value
Publication number	US-12051469-B2
Application number	US-202217825960-A
Country	US
Kind code	B2
Filing date	May 26, 2022
Priority date	Jul 23, 2020
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

First claim

What is claimed is:

1. An apparatus comprising control circuitry to:
implement an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck;
apply, immediately after a start of the erase operation, a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and
implement, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

2. The apparatus of claim 1 , wherein the control circuitry is to implement an erase-suspend operation on a deck being erased prior to applying the dummy read pulse.

3. The apparatus of claim 1 , wherein the one or more WLs include one of:
all WLs of the superblock, block or subblock including WLs of the erased deck and of the to-be-read deck;
only WLs of the one or more memory cells;
all WLs of all to-be-read decks of the superblock, block or subblock; or
WLs of decks of the memory device providing a path to a source or drain of the superblock, block or subblock.

4. The apparatus of claim 1 , wherein the control circuitry is to apply the dummy read pulse after a plurality of erase and read cycles with respect to the superblock, block or subblock, each erase and read cycle including an erase operation on a deck of the superblock, block or subblock that shares a pillar of the memory device with the one or more memory cells, and a read operation on the one or more memory cells.

5. A system including:
a three-dimensional non-volatile memory device a superblock, block or subblock including:
a plurality of decks stacked with respect to one another, each of the decks including a corresponding set of wordlines (WLs) and a corresponding set of interlayer dielectrics interposed between pairs of the corresponding set of WLs; and
a plurality of pillars intersecting the WLs and defining a plurality of memory cells therewith; and

a controller coupled to the memory device, the controller to:
implement an erase operation on a deck of the superblock, block or subblock to obtain an erased deck;
apply, immediately after a start of the erase operation, a dummy read pulse to one or more WLs of a to-be-read deck of the superblock, block or subblock; and
implement, after application of the dummy read pulse, a read operation on one or more memory cells of the plurality of memory cells to read data from the one or more memory cells, the one or more memory cells corresponding to the one or more WLs.

6. The system of claim 5 , wherein the controller is to apply the dummy read pulse at regular intervals after a predetermined number of erase and read cycles have been completed with respect to the superblock, block or subblock, each erase and read cycle including an erase operation on a deck of the superblock, block or subblock that shares a pillar of the memory device with the one or more memory cells, and a read operation on the one or more memory cells.

7. The system of claim 6 , wherein the predetermined number includes a number from 500 cycles up to 1000 cycles.

8. A method including:
implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck;
applying, immediately after a start of the erase operation, a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and
implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

9. The method of claim 8 , further including implementing an erase-suspend operation on a deck being erased prior to applying the dummy read pulse.

10. The method of claim 8 , further including applying the dummy read pulse in response to a determination that a read operation is to be implemented.

11. The method of claim 8 , wherein the one or more WLs include all WLs of the superblock, block or subblock including WLs of the erased deck and of the to-be-read deck.

12. The method of claim 8 , wherein the one or more WLs include only WLs of the one or more memory cells.

13. The method of claim 8 , wherein the one or more WLs include all WLs of all to-be-read decks of the superblock, block or subblock.

14. The method of claim 8 , wherein the one or more WLs further include WLs of decks of the memory device providing a path to a source or drain of the superblock, block or subblock.

15. The method of claim 8 , further including applying the dummy read pulse after a plurality of erase and read cycles with respect to the superblock, block or subblock, each erase and read cycle including an erase operation on a deck of the superblock, block or subblock that shares a pillar of the memory device with the one or more memory cells, and a read operation on the one or more memory cells.

16. The method of claim 15 , further including applying the dummy read pulse at regular intervals after a predetermined number of erase and read cycles have been completed with respect to the superblock, block or subblock, each erase and read cycle including an erase operation on a deck of the superblock, block or subblock that shares a pillar of the memory device with the one or more memory cells, and a read operation on the one or more memory cells.

17. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:
implement an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck;
apply, immediately after a start of the erase operation, a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and
implement, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

18. The machine readable storage medium of claim 17 , wherein the one or more WLs include one of:
all WLs of the superblock, block or subblock including WLs of the erased deck and of the to-be-read deck;
only WLs of the one or more memory cells;
all WLs of all to-be-read decks of the superblock, block or subblock; or
WLs of decks of the memory device providing a path to a source or drain of the superblock, block or subblock.

Assignees

• Intel NDTM US LLC

Inventors

• Cao Wei
• Fastow Richard M
• Yu Xuehong
• Sun Xin
• Kim Hyungseok
• Ramanan Narayanan
• Joshi Amol R
• Parat Krishna

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title