Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices

Patent metadata

Field	Value
Publication number	US-11355199-B2
Application number	US-202016947219-A
Country	US
Kind code	B2
Filing date	Jul 23, 2020
Priority date	Jul 23, 2020
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

First claim

What is claimed is:

1. An apparatus comprising control circuitry to:
implement an erase operation on a first deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck;
apply a dummy read pulse to one or more wordlines (WLs) of a second deck of the superblock, block or subblock, wherein the dummy read pulse includes a negative voltage pulse, and wherein the second deck:
includes a plurality of WLs including the one or more WLs, the plurality of WLs distinct from WLs of the first deck;
shares a plurality of pillars of the memory device with the first deck; and
includes memory cells of the non-volatile memory device that are to be read; and

implement, after application of the dummy read pulse to the one or more WLs of the second deck, a read operation on the memory cells of the second deck to read data from the one or more memory cells.

2. The apparatus of claim 1 , wherein the control circuitry is to implement an erase-suspend operation on the first deck prior to applying the dummy read pulse on the second deck.

3. The apparatus of claim 1 , wherein the control circuitry is to one of:
apply the dummy read pulse immediately after a start of the erase operation; or
apply the dummy read pulse in response to a determination that the read operation is to be implemented.

4. The apparatus of claim 1 , wherein the control circuitry is to one of:
apply the read dummy pulse to all WLs of the superblock, block or subblock including WLs of the first deck and of the second deck;
apply the read dummy pulse to only WLs of the one or more memory cells of the second deck;
apply dummy read pulse to all WLs of all to-be-read decks of the superblock, block or subblock; or
apply dummy read pulse to WLs of decks of the memory device providing a path to a source or drain of the superblock, block or subblock.

5. The apparatus of claim 1 , wherein the control circuitry is to apply the dummy read pulse to the one or more WLs of the second deck after a plurality of erase and read cycles with respect to the superblock, block or subblock, each erase and read cycle including an erase operation on a deck of the superblock, block or subblock that shares a pillar of the memory device with the one or more memory cells, and a read operation on one or more memory cells of the second deck.

6. A system including:
a three-dimensional non-volatile memory device a superblock, block or subblock including:
a plurality of decks stacked with respect to one another, each of the decks including a corresponding set of wordlines (WLs) and a corresponding set of interlayer dielectrics interposed between pairs of the corresponding set of WLs; and
a plurality of pillars intersecting the wordlines and defining a plurality of memory cells therewith; and

a controller coupled to the memory device, the controller to:
implement an erase operation on a first deck of the superblock, block or subblock to obtain an erased deck;
apply a dummy read pulse to one or more wordlines (WLs) of a second deck of the superblock, block or subblock, wherein the dummy read pulse includes a negative voltage pulse, and wherein the second deck:
includes a plurality of WLs including the one or more WLs, the plurality of WLs distinct from WLs of the first deck;
shares a plurality of pillars of the memory device with the first deck; and
includes memory cells of the non-volatile memory device that are to be read; and

implement, after application of the dummy read pulse to the one or more WLs of the second deck, a read operation on the memory cells of the second deck to read data from the one or more memory cells.

7. The system of claim 6 , wherein the controller is to apply the dummy read pulse at regular intervals after a predetermined number of erase and read cycles have been completed with respect to the superblock, block or subblock.

8. The system of claim 7 , wherein the predetermined number includes a number from 500 cycles up to 1000 cycles.

9. A method including:
implementing an erase operation on a first deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck;
applying a dummy read pulse to one or more wordlines (WLs) of a second deck of the superblock, block or subblock, wherein the dummy read pulse includes a negative voltage pulse, and wherein the second deck:
includes a plurality of WLs including the one or more WLs, the plurality of WLs distinct from WLs of the first deck;
shares a plurality of pillars of the memory device with the first deck; and
includes memory cells of the non-volatile memory device that are to be read; and

implementing, after application of the dummy read pulse to the one or more WLs of the second deck, a read operation on the memory cells of the second deck to read data from the one or more memory cells.

10. The method of claim 9 , further including implementing an erase-suspend operation on the first deck being erased prior to applying the dummy read pulse on the second deck.

11. The method of claim 9 , further including applying the dummy read pulse immediately after a start of the erase operation.

12. The method of claim 9 , further including applying the dummy read pulse in response to a determination that the read operation is to be implemented.

13. The method of claim 9 , further including applying the dummy read pulse to all WLs of the superblock, block or subblock including WLs of the erased deck and of the to-be-read deck.

14. The method of claim 9 , further including applying the dummy read pulse to only WLs of the second deck.

15. The method of claim 9 , further including applying the dummy read pulse to all WLs of all to-be-read decks of the superblock, block or subblock.

16. The method of claim 9 , further including applying the dummy read pulse to WLs of decks of the memory device providing a path to a source or drain of the superblock, block or subblock.

17. The method of claim 9 , further including applying the dummy read pulse to the one or more WLs of the second deck after a plurality of erase and read cycles with respect to the superblock, block or subblock, each erase and read cycle including an erase operation on a deck of the superblock, block or subblock that shares a pillar of the memory device with the one or more memory cells, and a read operation on one or more memory cells of the second deck.

18. The method of claim 17 , further including applying the dummy read pulse to the one or more WLs of the second deck at regular intervals after a predetermined number of erase and read cycles have been completed with respect to the superblock, block or subblock.

19. A non-transitory machine-readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:
implement an erase operation on a first deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck;
apply a dummy read pulse to one or more wordlines (WLs) of a second deck of the superblock, block or subblock, wherein the dummy read pulse includes a negative voltage pulse, and wherein the second deck:
includes a plurality of WLs including the one or more WLs, the plurality of WLs distinct from WLs of the first deck;
shares a plurality of pillars of the memory device with the first deck; and
includes memory cells of the non-volatile memory device that are to be read; and

implement, after application of the dummy read pulse t

Assignees

• Intel Corp

Inventors

• Cao Wei
• Fastow Richard M
• Yu Xuehong
• Sun Xin
• Kim Hyungseok
• Ramanan Narayanan
• Joshi Amol R
• Parat Krishna

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/32

  Timing circuits · CPC title