Memory cell sensing circuit with adjusted bias from pre-boost operation

Patent metadata

Field	Value
Publication number	US-12394492-B2
Application number	US-202017107679-A
Country	US
Kind code	B2
Filing date	Nov 30, 2020
Priority date	Nov 30, 2020
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.

First claim

What is claimed is:

1. A sense circuit comprising:
an output transistor to drive a sense output;
a sense node to drive a gate of the output transistor based on a value read from a memory cell;
a precharge circuit to precharge the sense node and the gate of the output transistor to a voltage reference prior to a sense operation; and
a boost circuit to boost the sense node, the boost circuit to be boosted up by a first boost voltage during precharge in which the sense node is precharged to the voltage reference, and the boost circuit to boost up the sense node after precharge to increase the voltage of the sense node by a second boost voltage greater than the first boost voltage, and discharge the sense node after the sense operation by a combination of the first boost voltage and the second boost voltage.

2. The sense circuit of claim 1 , wherein the boost circuit includes a boost capacitor having a top plate coupled to gate of the output transistor and a bottom plate coupled to a boost driver, wherein the boost driver is to boost the sense node through the boost capacitor.

3. The sense circuit of claim 1 , further comprising:
an isolation switch to selectively couple the sense node to the gate of the output transistor.

4. The sense circuit of claim 1 , further comprising:
a clamp switch, after the boost by the second boost voltage, to connect the value read from the memory cell to the sense node to discharge the sense node for a time Tsense.

5. The sense circuit of claim 4 , wherein the discharge from the second boost voltage comprises a discharge sufficient to read an SSPC (selective slow programming convergence) cell.

6. The sense circuit of claim 5 , wherein the boost circuit is further to boost up the sense node after discharge of the sense node, to return the sense node to a discharge level of a non-SSPC cell.

7. The sense circuit of claim 1 , wherein the memory cell comprises a 3D NAND (three-dimensional Not AND) memory cell.

8. The sense circuit of claim 7 , wherein the 3D NAND memory cell comprises a memory cell of one of multiple tiers of 3D NAND memory cells.

9. The sense circuit of claim 1 , wherein the memory cell comprises a 3D (three-dimensional) crosspoint memory cell.

10. The sense circuit of claim 1 , wherein the first boost voltage is a portion of a threshold voltage (Vt) of the output transistor, and the second boost voltage is greater than the Vt of the output transistor.

11. A storage device, comprising:
a three-dimensional (3D) memory array, including a string of bitlines; and
a sense circuit coupled to the string of bitlines, the sense circuit including
an output transistor to drive a sense output;
a sense node to conduct current to read a memory cell, the sense node to drive a gate of the output transistor;
a precharge circuit to precharge the sense node and the gate of the output transistor to a voltage reference prior to a sense operation; and
a boost circuit to boost the sense node, the boost circuit to be boosted up by a first boost voltage during precharge in which the sense node is precharged to the voltage reference, and the boost circuit to boost up the sense node after precharge to increase the voltage of the sense node by a second boost voltage greater than the first boost voltage, and discharge the sense node after the sense operation by a combination of the first boost voltage and the second boost voltage.

12. The storage device of claim 11 , wherein the boost circuit includes a boost capacitor having a top plate coupled to gate of the output transistor and a bottom plate coupled to a boost driver, wherein the boost driver is to boost the sense node through the boost capacitor.

13. The storage device of claim 11 , the sense circuit further comprising:
an isolation switch to selectively couple the sense node to the gate of the output transistor.

14. The storage device of claim 11 , the sense circuit further comprising:
a clamp switch, after the boost up by the second boost voltage, to connect the string of bitlines to the sense node to discharge the sense node from the second boost voltage for a time Tsense.

15. The storage device of claim 14 , wherein the discharge from the second boost voltage comprises a discharge sufficient to read an SSPC (selective slow programming convergence) cell.

16. The storage device of claim 11 , wherein the memory cell comprises a 3D NAND (three-dimensional Not AND) memory cell.

17. The storage device of claim 11 , wherein the memory cell comprises a 3D (three-dimensional) crosspoint memory cell.

18. The storage device of claim 11 , wherein the first boost voltage is a portion of a threshold voltage (Vt) of the output transistor, and the second boost voltage is greater than the Vt of the output transistor.

19. A method for sensing a memory cell, comprising:
precharging a sense node and a gate of an output transistor to a voltage reference prior to a sense operation;
boosting a boost circuit up by a first boost voltage during precharging;
boosting up the sense node with the boost circuit after precharge to increase the voltage of the sense node by a second boost voltage greater than the first boost voltage; and
discharging the sense node with the boost circuit after the sense operation by a combination of the first boost voltage and the second boost voltage.

20. The method of claim 19 , further comprising:
connecting the memory cell to the sense node after the boosting by the second boost voltage to discharge the sense node from the second boost voltage for a time Tsense sufficient to read an SSPC (selective slow programming convergence) cell.

21. The method of claim 20 , further comprising:
boosting the sense node after discharging the sense node, to return the sense node to a discharge level of a non-SSPC cell.

22. The method of claim 19 , wherein the first boost voltage is a portion of a threshold voltage (Vt) of the output transistor, and the second boost voltage is greater than the Vt of the output transistor.

Assignees

• Intel NDTM US LLC

Inventors

• Rajwade Shantanu R
• Nasri Bayan
• Fang Tzu-Ning
• Haque Rezaul
• Kulkarni Dhanashree R
• Ramanan Narayanan
• Amani Matin
• Rahman Ahsanur
• Park Seong Je
• Mahuli Netra

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24 Primary

  Bit-line control circuits · CPC title