NAND sensing circuit and technique for read-disturb mitigation

Patent metadata

Field	Value
Publication number	US-12266406-B2
Application number	US-202117202133-A
Country	US
Kind code	B2
Filing date	Mar 15, 2021
Priority date	Mar 15, 2021
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.

First claim

What is claimed is:

1. A NAND storage device comprising:
a storage array including a string of NAND memory cells coupled with a source line; and
circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation, the circuitry to:
charge the bitline of the string of NAND memory cells to a bitline voltage,
apply a first voltage to the source line that is higher than the bitline voltage,
enable a path between the bitline and a sensing node for current supplied to the bitline from the source line for a predetermined time, and
detect, after the predetermined time, a second voltage at a gate of a PMOS transistor at the sensing node, wherein the second voltage is indicative of a threshold voltage of a memory cell based on the current through the string from the source line to the bitline, and wherein the PMOS transistor is to operate in accumulation mode.

2. The NAND storage device of claim 1 , wherein:
the circuitry to perform the sensing operation includes PMOS transistors.

3. The NAND storage device of claim 2 , wherein the bitline voltage is a first bitline voltage, and wherein the NAND storage device further comprises:
an NMOS transistor between the bitline and the sensing node to bypass the circuitry to perform the sensing operation and supply a second bitline voltage to perform a program operation.

4. The NAND storage device of claim 1 , wherein:
the circuitry is to:
precharge the sensing node to a precharge voltage, and
prior to detection of the second voltage at the sensing node, cause a voltage decrease at the sensing node.

5. The NAND storage device of claim 4 , wherein:
after the voltage decrease, the sensing node is to be at a lower voltage than the precharge voltage.

6. The NAND storage device of claim 4 , wherein:
the circuitry is to:
after the detection of the second voltage, cause a voltage increase at the sensing node.

7. The NAND storage device of claim 6 , wherein:
the circuitry is to:
after the voltage increase, detect a third voltage at the sensing node.

8. The NAND storage device of claim 1 , wherein:
the PMOS transistor is a first PMOS transistor, and
the circuitry is to:
prior to detection of the second voltage at the sensing node:
turn on a second PMOS transistor between the bitline and the sensing node to enable the current to flow from the string to the sensing node for the predetermined time.

9. A system comprising:
a processor; and
a NAND storage device coupled with the processor, the NAND storage device including:
a storage array including a string of NAND memory cells coupled with a source line; and
circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation, the circuitry to:
charge the bitline of the string of NAND memory cells to a bitline voltage,
apply a first voltage to the source line that is higher than the bitline voltage,
enable a path between the bitline and a sensing node for current supplied to the bitline from the source line for a predetermined time, and
detect, after the predetermined time, a second voltage at a gate of a PMOS transistor at the sensing node, wherein the second voltage is indicative of a threshold voltage of a memory cell based on the current through the string from the source line to the bitline, and wherein the PMOS transistor is to operate in accumulation mode.

10. The system of claim 9 , wherein:
the circuitry to perform the sensing operation includes PMOS transistors.

11. The system of claim 10 , wherein the bitline voltage is a first bitline voltage, and wherein the system further comprises:
an NMOS transistor between the bitline and the sensing node to bypass the circuitry to perform the sensing operation and supply a second bitline voltage to perform a program operation.

12. The system of claim 9 , wherein:
the circuitry is to:
precharge the sensing node to a precharge voltage, and
prior to detection of the second voltage at the sensing node, cause a voltage decrease at the sensing node.

13. The system of claim 12 , wherein:
the circuitry is to:
after the detection of the second voltage, cause a voltage increase at the sensing node.

14. The system of claim 13 , wherein:
the circuitry is to:
after the voltage increase, detect a third voltage at the sensing node.

15. The system of claim 9 , wherein:
the PMOS transistor is a first PMOS transistor, and
the circuitry is to:
prior to detection of the second voltage at the sensing node:
turn on a second PMOS transistor between the bitline and the sensing node to enable the current to flow from the string to the sensing node for the predetermined time.

16. A solid state drive (SSD) comprising:
input/output (I/O) interface circuitry to couple with a host, the I/O interface circuitry to receive a read request; and
one or more dies, each of the one or more dies including:
a storage array including a string of NAND memory cells coupled with a source line; and
circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation in response to the read request, the circuitry to:
charge the bitline of the string of NAND memory cells to a bitline voltage,
apply a first voltage to the source line that is higher than the bitline voltage,
enable a path between the bitline and a sensing node for current supplied to the bitline from the source line for a predetermined time, and
detect, after the predetermined time, a second voltage at a gate of a PMOS transistor at the sensing node, wherein the second voltage is indicative of a threshold voltage of a memory cell based on the current through the string from the source line to the bitline, and wherein the PMOS transistor is to operate in accumulation mode.

17. The SSD of claim 16 , wherein:
the circuitry to perform the sensing operation includes PMOS transistors.

18. The SSD of claim 16 , wherein the bitline voltage is a first bitline voltage, and wherein the SSD further comprises:
an NMOS transistor between the bitline and the sensing node to bypass the circuitry to perform the sensing operation and supply a second bitline voltage to perform a program operation.

19. The SSD of claim 16 , wherein:
the circuitry is to:
precharge the sensing node to a precharge voltage, and
prior to detection of the second voltage at the sensing node, cause a voltage decrease at the sensing node.

20. The SSD of claim 19 , wherein:
the circuitry is to:
after the detection of the second voltage, cause a voltage increase at the sensing node.

Assignees

• Intel Corp
• Intel NDTM US LLC

Inventors

• Ramanan Narayanan

Classifications

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title