Configurable memory integrated circuit pins
US-2026051337-A1 · Feb 19, 2026 · US
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Prete Edoardo patents
Prete Edoardo is listed as an inventor on 23 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Prete Edoardo |
| Total patents | 23 |
| First publication | Nov 10, 2015 |
| Latest publication | Feb 19, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Receiver equalization circuitry using variable termination and T-coil
US-12388490-B2 · Aug 12, 2025 · US
Circuit element link training in a memory device
US-2025103424-A1 · Mar 27, 2025 · US
Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links
US-2025007516-A1 · Jan 2, 2025 · US
Periodic receiver clock data recovery with dynamic data edge
US-12174769-B2 · Dec 24, 2024 · US
Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links
US-12034440-B2 · Jul 9, 2024 · US
Clock frequency divider circuit
US-11860685-B2 · Jan 2, 2024 · US
Channel training using a replica lane
US-11805026-B2 · Oct 31, 2023 · US
Receiver equalization circuitry using variable termination and t-coil
US-2023308132-A1 · Sep 28, 2023 · US
Periodic receiver clock data recovery with dynamic data edge
US-2023305979-A1 · Sep 28, 2023 · US
Recent patents
Latest publications not already listed above.
Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links
US-2023134926-A1 · May 4, 2023 · US
Clock frequency divider circuit
US-2023136815-A1 · May 4, 2023 · US
Channel training using a replica lane
US-2021028995-A1 · Jan 28, 2021 · US
Channel training using a replica lane
US-10749756-B2 · Aug 18, 2020 · US
Low power VTT generation mechanism for receiver termination
US-10692545-B2 · Jun 23, 2020 · US
Low power vtt generation mechanism for receiver termination
US-2020098399-A1 · Mar 26, 2020 · US
Asynchronous feedback training
US-10103837-B2 · Oct 16, 2018 · US
Channel training using a replica lane
US-2017373944-A1 · Dec 28, 2017 · US
Asynchronous feedback training
US-2017373788-A1 · Dec 28, 2017 · US
Common mode extraction and tracking for data signaling
US-9673849-B1 · Jun 6, 2017 · US
Integrated controller for training memory physical layer interface
US-9639495-B2 · May 2, 2017 · US
Integrated controller for training memory physical layer interface
US-2015378603-A1 · Dec 31, 2015 · US
DDR receiver enable cycle training
US-9183125-B2 · Nov 10, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 23 |
| Ati Technologies Ulc | 6 |
| Brandl Kevin M | 1 |
| Housty Oswin E | 1 |
| Prete Edoardo | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04L7/043 | 6 |
| H04L7/10 | 6 |
| H04L25/14 | 6 |
| G06F13/1689 | 5 |
| H04L43/0823 | 4 |