Receiver equalization circuitry using variable termination and T-coil

Patent metadata

Field	Value
Publication number	US-12388490-B2
Application number	US-202217705022-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Mar 25, 2022
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. In order to better handle noise issues when using single-ended signaling, one or more of the receivers include equalization circuitry and termination circuitry. The termination circuitry prevents reflection on a corresponding transmission line ending at a corresponding receiver. The equalization circuitry uses a bridged T-coil circuit to provide continuous time linear equalization (CTLE) with no feedback loop. The equalization circuitry performs equalization by providing a high-pass filter that offsets the low-pass characteristics of a corresponding transmission line. A comparator of the receiver receives the input signal and compares it to a reference voltage. The placement of the comparator and the ratio of the inductances of the inductors of the bridged T-coil circuit are based on whether the receiver includes self-diagnostic circuitry.

First claim

What is claimed is:

1. A circuit comprising:
an input configured to receive a first signal from a transmission line comprising a metal trace with an impedance along the metal trace;
a first inductor coupled to receive the first signal from the input;
a second inductor connected in series with the first inductor, wherein a node between the first inductor and the second inductor comprises a capacitive load of circuitry that processes the first signal and at least one other signal within the circuit;
a termination resistor connected in series with the second inductor; and
a comparator configured to convey a second signal based on the first signal to circuitry of functional blocks.

2. The circuit as recited in claim 1 , further comprising electrostatic discharge (ESD) protection circuitry between the input and the first inductor, wherein the ESD protection circuitry is configured to clamp the first signal to a given range of voltages.

3. The circuit as recited in claim 1 , wherein the capacitive load of circuitry comprises a parasitic capacitive load of self-diagnostic circuitry.

4. The circuit as recited in claim 3 , wherein the termination resistor has a resistance that provides an impedance matching the impedance of the metal trace of the transmission line.

5. The circuit as recited in claim 3 , wherein a first inductance of the first inductor is equal to or greater than a second inductance of the second inductor.

6. The circuit as recited in claim 1 , wherein:
the comparator is configured to receive the first signal via the first inductor; and
the capacitive load of circuitry comprises an input capacitance of the comparator.

7. The circuit as recited in claim 6 , wherein a first inductance of the first inductor is less than a second inductance of the second inductor.

8. A method comprising:
receiving, by an input, a first signal from a transmission line comprising a metal trace with an impedance along the metal trace;
receiving, by a first inductor, the first signal from the input;
receiving, by a second inductor, the first signal via a series connection with the first inductor, wherein a node between the first inductor and the second inductor comprises a capacitive load of circuitry that processes the first signal and at least one other signal within a receiver that comprises the first inductor and the second inductor;
receiving, by a termination resistor, the first signal via a series connection with a series combination of the first inductor and the second inductor; and
conveying, by a comparator, a second signal based on the first signal to circuitry of functional blocks.

9. The method as recited in claim 8 , further comprising clamping the first signal to a given range of voltages by electrostatic discharge (ESD) protection circuitry between the input and the first inductor.

10. The method as recited in claim 8 , wherein the capacitive load of circuitry comprises a parasitic capacitive load of self-diagnostic circuitry.

11. The method as recited in claim 10 , wherein the termination resistor has a resistance that provides an impedance matching the impedance of the metal trace of the transmission line.

12. The method as recited in claim 10 , wherein a first inductance of the first inductor is equal to or greater than a second inductance of the second inductor.

13. The method as recited in claim 8 , further comprising receiving, by the comparator, the first signal via the first inductor, wherein the capacitive load of circuitry comprises an input capacitance of the comparator.

14. The method as recited in claim 13 , wherein a first inductance of the first inductor is less than a second inductance of the second inductor.

15. An apparatus comprising:
a plurality of receivers configured to receive signals; and
a plurality of transmitters configured to send a plurality of signals to the plurality of receivers via a plurality of transmission lines, each comprising a metal trace with a corresponding impedance along the metal trace;
wherein a given receiver of the plurality of receivers is configured to receive a first signal of the plurality of signals from a given transmitter of the plurality of transmitters; and
wherein the given receiver comprises:
an input configured to receive the first signal from the given transmitter via a transmission line of the plurality of transmission lines;
a first inductor coupled to receive the first signal from the input;
a second inductor connected in series with the first inductor, wherein a node between the first inductor and the second inductor comprises a capacitive load of circuitry of the given receiver that processes the first signal and at least one other signal within the given receiver;
a termination resistor connected in series with the second inductor; and
a comparator configured to convey a second signal based on the first signal to circuitry of functional blocks.

16. The apparatus as recited in claim 15 , wherein the capacitive load of circuitry comprises a parasitic capacitive load of self-diagnostic circuitry.

17. The apparatus as recited in claim 16 , wherein the termination resistor has a resistance that provides an impedance matching the impedance of the metal trace of the transmission line.

18. The apparatus as recited in claim 16 , wherein a first inductance of the first inductor is equal to or greater than a second inductance of the second inductor.

19. The apparatus as recited in claim 15 , wherein:
the comparator is configured to receive the first signal via the first inductor; and
the capacitive load of circuitry comprises an input capacitance of the comparator.

20. The apparatus as recited in claim 19 , wherein a first inductance of the first inductor is less than a second inductance of the second inductor.

Assignees

• Advanced Micro Devices Inc

Inventors

• Gonzales Dean E
• Prete Edoardo
• Paraschou Milam
• Chirachanchai Mark
• Talbot Gerald R

Classifications

• H04B3/26

  Improving frequency characteristic by the use of loading coils · CPC title

• H04B3/46 Primary

  Monitoring; Testing · CPC title

• H01F17/08

  Loading coils for telecommunication circuits · CPC title

• H04B3/145

  variable equalisers · CPC title

• H04B3/141 Primary

  using multiequalisers, e.g. bump, cosine, Bode · CPC title