Asynchronous feedback training

Patent metadata

Field	Value
Publication number	US-10103837-B2
Application number	US-201615191322-A
Country	US
Kind code	B2
Filing date	Jun 23, 2016
Priority date	Jun 23, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.

First claim

What is claimed is:

1. A system comprising:
a transmitter; and
a receiver coupled to the transmitter via a communication channel including one or more data lanes;
wherein the transmitter is configured to:
initiate an asynchronous feedback training sequence by transmitting a training sequence indication as a plurality of bits during a supercycle comprising a first multi-bit sequence followed by a second multi-bit sequence, where the first multi-bit sequence and the second multi-bit sequence are of opposite polarity and a transition from the first multi-bit sequence to the second multi-bit sequence occurs at a midpoint of the supercycle; and
transmit a test pattern on a first lane of the channel at the end of the supercycle; and

wherein the receiver is configured to:
receive the training sequence indication;
sample a state of the first lane at an end of each supercycle;
responsive to determining that a transition occurs on the first lane between two successive tests:
sample the state of the first lane at an end of each supercycle;
if the state of the first lane does not change for a predetermined number of samples, determine the training sequence indication has been detected; and
if the state of the first lane does change during the predetermined number of samples, determine the training sequence indication has not been detected;

capture the test pattern responsive to detecting the training sequence indication; and
convey an error indication to the transmitter via the first lane that indicates whether any errors were detected in the test pattern;

wherein each of the transmitter and the receiver includes a supercycle counter for counting supercycles, with a single supercycle corresponding to N clock cycles of a system clock, where N is an integer greater than 1.

2. The system as recited in claim 1 , wherein responsive to receiving the error indication, the transmitter is configured to change a delay setting for the first lane if the error indication indicates an error was detected.

3. The system as recited in claim 1 , wherein the transmitter uses a first system clock for counting supercycles and the receiver uses a second system clock different from the first system clock for counting supercycles.

4. The system as recited in claim 1 , wherein the receiver is configured to determine when to capture the test pattern sequence by using the training sequence indication to identify the supercycle.

5. The system as recited in claim 1 , wherein the error indication is a single bit.

6. An apparatus comprising:
a transmitter;
a receiver; and
a communication channel comprising a plurality of data lanes;
wherein the transmitter is configured to:
initiate an asynchronous feedback training sequence by transmitting a training sequence indication as a plurality of bits during a supercycle comprising a first multi-bit sequence followed by a second multi-bit sequence, where the first multi-bit sequence and the second multi-bit sequence are of opposite polarity and a transition from the first multi-bit sequence to the second multi-bit sequence occurs at a midpoint of the supercycle; and
transmit a test pattern on each lane of the plurality of lanes; and

wherein the receiver is configured to:
receive the training sequence indication;
sample a state of the first lane at an end of each supercycle;
responsive to determining that a transition occurs on the first lane between two successive tests:
sample the state of the first lane at an end of each supercycle;
if the state of the first lane does not change for a predetermined number of samples, determine the training sequence indication has been detected; and
if the state of the first lane does change during the predetermined number of samples, determine the training sequence indication has not been detected;
capture the test pattern responsive to detecting the training sequence indication; and
convey an error indication to the transmitter via the first lane that indicates whether any errors were detected in the test pattern;

wherein each of the transmitter and the receiver includes a supercycle counter for counting supercycles, with a single supercycle corresponding to N clock cycles of a system clock, where N is an integer greater than 1.

7. The apparatus as recited in claim 6 , wherein the transmitter comprises:
a separate delay unit comprising circuitry for each of the plurality of lanes; and
a single delay unit configured to apply a single delay setting to a group of lanes of the plurality of lanes.

8. The apparatus as recited in claim 6 , wherein the transmitter uses a first system clock for counting supercycles and the receiver uses a second system clock different from the first system clock for counting supercycles.

9. The apparatus as recited in claim 6 , wherein the receiver is configured to determine when to capture the test pattern sequence by using the training sequence indication to identify the supercycle.

10. The apparatus as recited in claim 6 , wherein the error indication is a single bit.

11. A method comprising:
initiating, by a transmitter, an asynchronous feedback training sequence indication as a plurality of bits during a supercycle comprising a first multi-bit sequence followed by a second multi-bit sequence, where the first multi-bit sequence and the second multi-bit sequence are of opposite polarity and a transition from the first multi-bit sequence to the second multi-bit sequence occurs at a midpoint of the supercycle;
transmitting a test pattern to a receiver on a first lane of a channel;
receiving, by the receiver, the training sequence indication; and
sampling a state of the first lane at an end of each supercycle;
responsive to determining that a transition occurs on the first lane between two successive tests:
sampling the state of the first lane at an end of each supercycle;
if the state of the first lane does not change for a predetermined number of samples, determining the training sequence indication has been detected; and
if the state of the first lane does change during the predetermined number of samples, determining the training sequence indication has not been detected;

capturing the test pattern responsive to detecting the training sequence indication;
conveying an error indication to the transmitter via the first lane that indicates whether any errors were detected in the test pattern;
wherein each of the transmitter and the receiver includes a supercycle counter for counting supercycles, with a single supercycle corresponding to N clock cycles of a system clock, where N is an integer greater than 1.

12. The method as recited in claim 11 , further comprising changing a delay setting for the first lane if the error indication indicates an error was detected responsive to receiving the error indication.

13. The method as recited in claim 11 , further comprising the transmitter using a first system clock for counting supercycles and the receiver using a second system clock different from the first system clock for counting supercycles.

14. The method as recited in claim 11 , wherein the method further comprising determining when to capture the test pattern sequence by using the training sequence indication to identify the supercycle.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Lackey Jr Stanley Ames
• Tohidi Damon
• Talbot Gerald R
• Prete Edoardo

Classifications

• H04L2012/5681

  Buffer or queue management · CPC title

• H04L1/0073

  Special arrangements for feedback channel · CPC title

• H04L1/0002 Primary

  by adapting the transmission rate · CPC title

• H04L7/0037

  Delay of clock signal · CPC title

• H04L7/10 Primary

  Arrangements for initial synchronisation · CPC title