Integrated controller for training memory physical layer interface

Patent metadata

Field	Value
Publication number	US-9639495-B2
Application number	US-201414318114-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Jun 27, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

First claim

What is claimed is:

1. An apparatus comprising:
a memory physical layer interface (PHY) to couple to an external memory, the memory PHY comprising a controller, wherein the controller is to control training of the memory PHY for communication with the external memory based on a training algorithm so as to converge on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

2. The apparatus of claim 1 , wherein the training algorithm is a seedless training algorithm.

3. An apparatus comprising:
a memory physical layer interface (PHY) to couple to an external memory, the memory PHY comprising a controller, wherein the controller is to control training of the memory PHY for communication with the external memory based on a training algorithm; and
a first training engine to generate at-speed programmable sequences of commands for delivery to the external memory in response to control signaling generated by the controller based on the training algorithm.

4. The apparatus of claim 3 , further comprising:
a second training engine to generate training data sequences for delivery to the external memory in response to control signaling generated by the first training engine.

5. The apparatus of claim 4 , further comprising:
a third training engine to compare sequences received from the external memory to the training sequences generated by the second training engine.

6. The apparatus of claim 5 , wherein the first training engine sequences execution of tasks performed by at least one of the second training engine and the third training engine based on the training algorithm.

7. The apparatus of claim 5 , wherein the third training engine adjusts at least one of a timing parameter and a voltage offset parameter used by the memory PHY for at least one of reading data from the external memory and writing data to the external memory.

8. The apparatus of claim 7 , wherein the third training engine determines at least one of the timing parameter and the voltage offset parameter based on numbers of correct samples and incorrect samples in sampled training data.

9. The apparatus of claim 3 , wherein the training algorithm is a seedless training algorithm.

10. A method comprising:
generating, at a controller that is included in a memory physical layer interface (PHY), control signaling for training of the memory PHY for communication with an external memory based on a training algorithm, wherein generating the control signaling comprises generating the control signaling so that the training algorithm converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

11. The method of claim 10 , wherein generating the control signaling comprises generating the control signaling based on a seedless training algorithm.

12. A method comprising:
generating, at a controller that is included in a memory physical layer interface (PHY), control signaling for training of the memory PHY for communication with an external memory based on a training algorithm; and
providing first control signaling from the controller to a first training engine, wherein the first training engine is to generate sequences of at-speed commands for delivery to the external memory in response to the first control signaling.

13. The method of claim 12 , further comprising:
providing second control signaling from the first training engine to a second training engine, wherein the second training engine is to generate training sequences for delivery to the external memory in response to the second control signaling from the first training engine.

14. The method of claim 13 , further comprising:
providing third control signaling from the first training engine to a third training engine, wherein the third training engine is to compare sequences received from the external memory to the training sequences generated by the second training engine in response to the third control signaling.

15. The method of claim 14 , further comprising:
sequencing execution of tasks performed by at least one of the second training engine and the third training engine based on signals provided to said at least one of the second training engine and the third training engine by the first training engine.

16. The method of claim 14 , further comprising:
determining, at the third training engine, at least one of a timing delay and a voltage offset used by the memory PHY for at least one of reading data from the external memory and writing data to the external memory.

17. The method of claim 16 , wherein determining said at least one of the timing delay and the voltage offset comprises determining said at least one of the timing delay and the voltage offset based on a predetermined ratio of correct samples to incorrect samples in sampled training data.

18. The method of claim 12 , wherein generating the control signaling comprises generating the control signaling based on a seedless training algorithm.

19. A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
generate control signaling for training of the memory physical layer interface (PHY) for communication with an external memory based on a training algorithm, wherein the memory PHY includes said at least one processor, wherein said at least one processor is to generate the control signaling based on a seedless training algorithm so that the seedless training algorithm converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

Assignees

• Advanced Micro Devices Inc

Inventors

• Dearth Glenn A
• Talbot Gerry
• Kashem Anwar
• Prete Edoardo
• Amick Brian

Classifications

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title