Floating-point conversion with denormalization
US-12585430-B2 · Mar 24, 2026 · US
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Payer Stefan patents
Payer Stefan is listed as an inventor on 53 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Payer Stefan |
| Total patents | 53 |
| First publication | Jul 11, 2017 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Dynamic algorithm selection
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Rounding hexadecimal floating point numbers using binary incrementors
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Verifying the correctness of a leading zero counter
US-12056465-B2 · Aug 6, 2024 · US
Method for Producing Structured Layers for Materials for Producing Dental Prostheses, and Device for This Purpose
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Method to limit the time a semiconductor device operates above a maximum operating voltage
US-11817697-B2 · Nov 14, 2023 · US
Verifying the correctness of a leading zero counter
US-2023315394-A1 · Oct 5, 2023 · US
Method to limit the time a semiconductor device operates above a maximum operating voltage
US-2023318286-A1 · Oct 5, 2023 · US
Rounding hexadecimal floating point numbers using binary incrementors
US-2023315386-A1 · Oct 5, 2023 · US
Reduced logic conversion of binary integers to binary coded decimals
US-2023308113-A1 · Sep 28, 2023 · US
Recent patents
Latest publications not already listed above.
Floating-point conversion with denormalization
US-2023297334-A1 · Sep 21, 2023 · US
Hardware device to execute instruction to convert input value from one data format to another data format
US-2023289139-A1 · Sep 14, 2023 · US
Hardware device to execute instruction to convert input value from one data format to another data format
US-2023289138-A1 · Sep 14, 2023 · US
Dynamic algorithm selection
US-2023273769-A1 · Aug 31, 2023 · US
Vector string search instruction
US-11663270-B2 · May 30, 2023 · US
Hexadecimal floating point multiply and add instruction
US-11531546-B2 · Dec 20, 2022 · US
Hexadecimal floating point multiply and add instruction
US-2022283818-A1 · Sep 8, 2022 · US
Instruction scheduling during execution in a processor
US-11256511-B2 · Feb 22, 2022 · US
Parallel rounding for conversion from binary floating point to binary coded decimal
US-11221826-B2 · Jan 11, 2022 · US
Parallelized rounding for decimal floating point to binary coded decimal conversion
US-11210064-B2 · Dec 28, 2021 · US
Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback
US-11175921-B2 · Nov 16, 2021 · US
Fault-tolerant clock gating
US-11099602-B2 · Aug 24, 2021 · US
Vector string search instruction
US-2021232638-A1 · Jul 29, 2021 · US
Vector string search instruction
US-11068541-B2 · Jul 20, 2021 · US
Plausability-driven fault detection in result logic and condition codes for fast exact substring match
US-11042371-B2 · Jun 22, 2021 · US
Plausibility-driven fault detection in string termination logic for fast exact substring match
US-10996951-B2 · May 4, 2021 · US
Method and apparatus for wiring multiple technology evaluation circuits
US-10983159-B2 · Apr 20, 2021 · US
Plausability-driven fault detection in string termination logic for fast exact substring match
US-2021072989-A1 · Mar 11, 2021 · US
Plausability-driven fault detection in result logic and condition codes for fast exact substring match
US-2021072990-A1 · Mar 11, 2021 · US
Parallel rounding for conversion from binary floating point to binary coded decimal
US-2021034329-A1 · Feb 4, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 52 |
| Kulzer & Co Gmbh | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30036 | 13 |
| G06F16/90344 | 11 |
| G06F9/30021 | 11 |
| G06F9/30018 | 11 |
| G06F9/30038 | 11 |