Parallelized rounding for decimal floating point to binary coded decimal conversion

Patent metadata

Field	Value
Publication number	US-11210064-B2
Application number	US-201916525720-A
Country	US
Kind code	B2
Filing date	Jul 30, 2019
Priority date	Jul 30, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, using a processor, a decimal floating point number; and
using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

2. The method according to claim 1 , wherein the floating point unit finishes the rounding loop and outputs a result of the rounding loop.

3. The method according to claim 1 , wherein the floating point unit uses a pipeline having a first plurality of stages as part of the conversion loop.

4. The method according to claim 3 , wherein the pipeline further includes a first plurality of shift registers as part of the conversion loop.

5. The method according to claim 4 , wherein the pipeline further includes a second plurality of stages as part of the rounding loop.

6. The method according to claim 5 , wherein the pipeline further includes a second plurality of shift registers as part of the rounding loop.

7. The method according to claim 1 , wherein the conversion loop uses a conversion register which outputs a result which is added to the rounding loop.

8. A system comprising one or more processors for executing computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
receiving a decimal floating point number; and
converting, by a floating point unit within the one or more processors, the decimal floating point number into a binary coded decimal number, wherein the converting is performed by a conversion loop that is started subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

9. The system according to claim 8 , wherein the floating point unit finishes the rounding loop and outputs a result of the rounding loop.

10. The system according to claim 8 , wherein the floating point unit uses a pipeline having a first plurality of stages as part of the conversion loop.

11. The system according to claim 10 , wherein the pipeline further includes a first plurality of shift registers as part of the conversion loop.

12. The system according to claim 11 , wherein the pipeline further includes a second plurality of stages as part of the rounding loop.

13. The system according to claim 12 , wherein the pipeline further includes a second plurality of shift registers as part of the rounding loop.

14. The system according to claim 8 , wherein the conversion loop uses a conversion register which outputs a result which is added to the rounding loop.

15. A computer program product comprising:
one or more computer-readable storage media, wherein the one or more computer-readable storage media are not transitory signals per se;
first program instructions, stored on at least one of the one or more computer-readable storage media, to receive a decimal floating point number using a processor; and
second program instructions, stored on at least one of the one or more computer-readable storage media, to cause a floating point unit to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

16. The computer program product according to claim 15 , wherein the floating point unit finishes the rounding loop with a result of the rounding loop.

17. The computer program product according to claim 15 , wherein the floating point unit uses a pipeline having a first plurality of stages as part of the conversion loop.

18. The computer program product according to claim 17 , wherein the pipeline further includes a first plurality of shift registers as part of the conversion loop.

19. The computer program product according to claim 18 , wherein the pipeline further includes a second plurality of stages as part of the rounding loop.

20. The computer program product according to claim 15 , wherein the conversion loop uses a conversion register which outputs a result which is added to the rounding loop.

Assignees

• IBM

Inventors

• Payer Stefan
• Mueller Silvia Melitta
• Hofmann Nicol
• Figuli Razvan Peter

Classifications

• H03M7/12

  having two radices, e.g. binary-coded-decimal code · CPC title

• H03M7/24

  Conversion to or from floating-point codes · CPC title

• G06F7/49947 Primary

  Rounding · CPC title