Fault-tolerant clock gating

Patent metadata

Field	Value
Publication number	US-11099602-B2
Application number	US-201916398793-A
Country	US
Kind code	B2
Filing date	Apr 30, 2019
Priority date	Apr 30, 2019
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

First claim

What is claimed is:

1. A method, comprising:
obtaining a trigger signal directed to a component in a subset of components of an electronic circuit;
activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal;
determining an active period based on the trigger signal, wherein the clock remains active for the active period;
initiating one of a timer or counter for the active period, wherein a limit is defined for the one of the timer or counter;
dynamically extending the active period for a busy period after the one of the timer or counter is initiated; and
deactivating the clock following the active period.

2. The method according to claim 1 , further comprising initiating or extending the active period based on a switch that indicates a fault in the clock gating.

3. The method according to claim 2 , wherein the initiating or extending the active period includes ensuring that the clock remains active.

4. The method according to claim 1 , further comprising setting a buffer period such that the clock remains active for the buffer period after termination of the active phase.

5. The method according to claim 4 , wherein the setting the buffer period is based on the busy period resulting from a multi-cycle operation.

6. The method according to claim 1 , wherein the dynamically extending the active period for the busy period is based on an additional trigger signal being directed to the subset of components of the electronic circuit.

7. The method according to claim 1 , wherein the dynamically extending the active period for the busy period is based on executing a multi-cycle operation.

8. The method according to claim 1 , wherein the dynamically extending the active period for the busy period is based on the one of the timer or counter not yet reaching the limit.

9. A processor, comprising:
a portion including a clock;
a clock gate circuit configured to control activation of the clock, the clock gate circuit configured to set one of a timer or counter for a specified period to activate the clock for the specified period based on a trigger signal and to dynamically extend the specified period for a busy period, during tolling of the specified period, based on one or more conditions.

10. The processor according to claim 9 , wherein the clock gate circuit includes a trigger module with an OR gate configured to receive the trigger signal as one of a plurality of predefined triggers and a preliminary module with one or more flip-flops configured to activate the clock for a preliminary period prior to the setting of the one of the timer or counter.

11. The processor according to claim 9 , wherein the clock gate circuit includes a count and encode module with a look-up table configured to output a binary code to activate the clock for the specified period and the busy period.

12. The processor according to claim 9 , wherein the clock gate circuit includes a dynamic extension module configured to determine the busy period based on execution of a multi-cycle operation by the processor.

13. The processor according to claim 9 , wherein the one or more conditions include another trigger signal being received by the clock gate circuit.

14. The processor according to claim 9 , wherein the one or more conditions include a multi-cycle operation being executed by the portion of the processor.

15. The processor according to claim 9 , wherein the one or more conditions include the specified period not being completed.

16. A clock gating circuit in a processor, comprising:
a count and encode module configured to set one of a timer or counter for a specified period to activate the clock for the specified period based on a trigger signal; and
a dynamic extension module configured to dynamically extend the specified period for a busy period, during tolling of the specified period, based on one or more conditions.

17. The clock gating circuit according to claim 16 , further comprising a preliminary module configured to activate the clock for a preliminary period prior to initiation of the one of the timer or counter for the specified period.

18. The clock gating circuit according to claim 16 , further comprising a trigger module with an OR gate configured to receive the trigger signal as one of a plurality of predefined triggers.

19. The clock gating circuit according to claim 16 , wherein the count and encode module includes a look-up table configured to output a binary code to activate the clock for the specified period and the busy period.

20. The clock gating circuit according to claim 16 , wherein the one or more conditions include another trigger signal being received by the clock gate circuit, a multi-cycle operation being executed by the processor, and the specified period not being completed.

Assignees

• IBM

Inventors

• Figuli Razvan Peter
• Lichtenau Cedric
• Payer Stefan
• Klein Michael

Classifications

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K21/10

  comprising logic circuits · CPC title