Rounding hexadecimal floating point numbers using binary incrementors

Patent metadata

Field	Value
Publication number	US-12190078-B2
Application number	US-202217705036-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Mar 25, 2022
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

First claim

What is claimed is:

1. A method of rounding hexadecimal floating point numbers using binary incrementors, the method comprising:
incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
incrementing, by a second incrementor, a second subset of bits of the operand;
generating, by a multiplexor, an intermediate result based on a carryout of the second incrementor;
generating, by correction logic if a carryout of the first incrementor is set, an incremented result based on the carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor; and
generating, by the correction logic if the carryout of the first incrementor is not set, the incremented result based on whether the first bit of the intermediate result is set.

2. The method of claim 1 , wherein generating the intermediate result comprises:
including, in the intermediate result, a non-incremented first subset of bits of the operand responsive to the carryout of the second incrementor not being set;
including, in the intermediate result, an incremented first subset of bits of the operand responsive to the carryout of the second incrementor being set; and
including, in the intermediate result, an incremented second subset of bits of the operand.

3. The method of claim 1 , wherein generating the incremented result comprises:
responsive to the carryout of the first incrementor being set and the carryout of the second incrementor being set:
generating, as a fraction component of the incremented result, a first predefined portion of leading bits and the intermediate result excluding an output of the second incrementor; and
incrementing an exponent component of the operand.

4. The method of claim 1 , wherein generating the incremented result comprises:
responsive to the carryout of the first incrementor not being set and the first bit of the intermediate result being set:
generating, as a fraction component of the incremented result, a second predefined portion of leading bits and the intermediate result excluding an output of the second incrementor; and
incrementing an exponent component of the operand.

5. The method of claim 1 , wherein generating the incremented result comprises:
responsive to the carryout of the first incrementor not being set and the first bit of the intermediate result not being set, generating, as a fraction component of the incremented result, the intermediate result excluding the first bit of the intermediate result.

6. The method of claim 1 , wherein the second subset of bits of the operand comprises a four least significant bits of the operand.

7. The method of claim 6 , wherein the second incrementor comprises a four-bit incrementor.

8. The method of claim 1 , wherein the first incrementor comprises a fifty-three-bit incrementor.

9. A chip for rounding hexadecimal floating point numbers using binary incrementors, comprising:
a first incrementor;
a second incrementor;
correction logic; and
a multiplexor, wherein:
the first incrementor increments a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
the second incrementor increments a second subset of bits of the operand;
the multiplexor receives a non-incremented first subset of bits and the incremented first subset of bits and generates an intermediate result based on a carryout of the second incrementor;
the correction logic generates an incremented result if a carryout of the first incrementor is set based on the carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor; and
the correction logic generates the incremented result if the carryout of the first incrementor is not set based on whether the first bit of the intermediate result is set.

10. The chip of claim 9 , wherein the multiplexor generates the intermediate result by:
including, in the intermediate result, the non-incremented first subset of bits of the operand responsive to the carryout of the second incrementor not being set;
including, in the intermediate result, the incremented first subset of bits of the operand responsive to the carryout of the second incrementor being set; and
including, in the intermediate result, the incremented second subset of bits of the operand.

11. The chip of claim 9 , wherein the correction logic generates the incremented result by:
responsive to the carryout of the first incrementor being set and the carryout of the second incrementor being set:
generating, as a fraction component of the incremented result, a first predefined portion of leading bits and the intermediate result excluding an output of the second incrementor; and
incrementing an exponent component of the operand.

12. The chip of claim 9 , wherein the correction logic generates the incremented result by:
responsive to the carryout of the first incrementor not being set and the first bit of the intermediate result being set:
generating, as a fraction component of the incremented result, a second predefined portion of leading bits and the intermediate result excluding an output of the second incrementor; and
incrementing an exponent component of the operand.

13. The chip of claim 9 , wherein the correction logic generates the incremented result by:
responsive to the carryout of the first incrementor not being set and the first bit of the intermediate result not being set, generating, as a fraction component of the incremented result, the intermediate result excluding the first bit of the intermediate result.

14. The chip of claim 9 , wherein the second subset of bits of the operand comprises a four least significant bits of the operand.

15. The chip of claim 14 , wherein the second incrementor comprises a four-bit incrementor.

16. The chip of claim 9 , wherein the first incrementor comprises a fifty-three-bit incrementor.

17. An apparatus for comprising:
a processor; and
memory coupled to the processor, wherein the processor comprises:
a first incrementor;
a second incrementor;
correction logic; and
a multiplexor, and wherein:
the first incrementor increments a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
the second incrementor increments a second subset of bits of the operand;
the multiplexor receives a non-incremented first subset of bits and the incremented first subset of bits and generates an intermediate result based on a carryout of the second incrementor;
the correction logic generates an incremented result if a carryout of the first incrementor is set based on the carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor; and
the correction logic generates the incremented result if the carryout of the first incrementor is not set based on whether the first bit of the intermediate result is set.

18. The apparatus of claim 17 , wherein the multiplexor generates the intermediate result by:
including, in the intermediate result, the non-incremented first subset of bits of the operand responsive to the carryout of the second incrementor not being set;
including, in the intermediate result, the incremented first subset of bits of the operand responsive to the carryout of the second incrementor being set; and
including, in the intermediate result, the incremented second subset of bits of the operand.

Assignees

• IBM

Inventors

• Klein Michael
• Leber Petra
• Lichtenau Cedric
• Payer Stefan
• Schelm Kerstin Claudia

Classifications

• G06F2207/3844

  Hexadecimal · CPC title

• G06F7/4836 Primary

  Computations with rational numbers · CPC title

• G06F7/74

  Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders {(with shifting G06F5/01)} · CPC title

• G06F7/49947 Primary

  Rounding · CPC title