Method and apparatus for wiring multiple technology evaluation circuits

Patent metadata

Field	Value
Publication number	US-10983159-B2
Application number	US-201816226942-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Dec 20, 2018
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

A system, apparatus, and method of testing a plurality of test circuits is disclosed that includes inputting experiment data to the plurality of test circuits; applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits. The method in an aspect further comprises reading out a data out signal from each of the plurality of test circuits; and shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.

First claim

What is claimed is:

1. A method of testing a plurality of test circuits comprising:
inputting experiment data to the plurality of test circuits;
applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and
shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits,
wherein the control signal comprises a bit field and shifting the control signal includes changing the most significant digit (MSD) in the bit field of the control signal to be the least significant digit (LSD) in the bit field, and shifting the remaining bits in the bit field one place to the left.

2. The method if claim 1 , wherein inputting experiment data to the plurality of test circuits includes connecting an input signal line to each of the plurality of test circuits.

3. The method according to claim 2 , wherein inputting experiment data includes encoding all the experiment data on the input signal line.

4. The method according to claim 1 , wherein applying a control signal to the plurality of test circuits includes connecting the same one or more bits of a bus to each of the plurality of test circuits.

5. The method according to claim 4 , wherein applying a control signal to each of the plurality of test circuits includes applying the lowest one or more bits of the control signal to each of the plurality of test circuits.

6. The method of claim 1 , wherein the experiment data includes first experiment data representative of a first experiment and second experiment data representative of a second experiment, and wherein the first experiment data is applied to all the plurality of test circuits prior to the second experiment data being applied to any of the plurality of test circuits.

7. The method of claim 1 , wherein the control signal comprises a plurality of bits.

8. The method of claim 1 , wherein a control signal line for carrying the control signal connects to the plurality of test circuits and shifting the control signal is performed by a plurality of shifters connected to the control signal line wherein one shifter is connected after each of the plurality of test circuits.

9. The method of claim 1 , further comprising:
reading out a data out signal from each of the plurality of test circuits; and
shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.

10. The method of claim 9 , wherein reading out the data out signal from each of the plurality of test circuits includes connecting the same one or more bits of a bus to each of the plurality of test circuits.

11. A system for testing a group of test circuits formed on a silicon chip together, comprising:
a load input line to input experiment data to each of the plurality of test circuits, the load data input line connectible to each of the group of circuits;
a control signal bus to receive and carry a control signal that control the application of the experiment data, the control signal bus connectable to each of the plurality of test circuits; and
a plurality of shifters, one shifter for each test circuit in the group of test circuits to be tested together, each shifter connected to the control signal bus at a position after each test circuit of the group of test circuits, wherein each shifter is configured to shift a bit field applied to the shifter,
wherein the shifter has a plurality of input lines and a plurality of output lines, the number of input lines equal to the number of output lines and equal to the number n bits of the control signal bus; wherein a first input line connects to an n last output line, and each subsequent input line connects to an (n−1) output line such that a bit field fed into the shifter is shifted so that its most significant digit (MSD) is output as the least significant digit (LSD) and all other bits in the bit field are shifter one place to the left.

12. The system of claim 11 , wherein the group of test circuits are connected to the control signal bus at the same one or more bits, and wherein one of the shifters is connected to the control signal bus after each test circuit on the control signal bus.

13. The method of claim 11 , wherein the control signal bus is a multi-bit bus and the system is configured so that the control signal bus is connectable to each of the plurality of test circuits at the same one of more bits.

14. The system of claim 11 , further comprising:
a data out bus to receive the output from the plurality of test circuits, the data out bus connectable to each of the plurality of test circuits; and
a plurality of shifters, one shifter for each test circuit in the group of test circuits to be tested together, each shifter connected to the data out bus at a position after each test circuit of the group of test circuits, wherein each shifter is configured to shift a bit field applied to the shifter.

15. The system of claim 14 , wherein the data out bus is a multi-bit bus and the system is configured so that the control signal bus is connectable to each of test circuits of the group of test circuits at the same one or more bits.

16. The system of claim 14 , wherein the group of test circuits are connected to the load data input line, the control signal bus, and the data out bus, and the group of test circuits are connected to the control signal bus and to the data out bus at the same one or more bits, and one of the shifters is connected to the control signal bus after each test circuit on the control signal bus, and one of the shifters is connected to the data out bus after each test circuit on the data out bus.

17. An apparatus for testing a plurality of test circuits by shifting i input bits of an f bit field where i<f, the apparatus comprising:
f input lines connected to f output lines, wherein the first i input lines are connected to the last i output lines, and the remaining input lines (f−i) are to connected to remaining output lines (f−i) in a manner to shift the bit field i bits to the left,
wherein the apparatus outputs a bit field where each of the bits of the input bit field other than the most significant digit (MSD) is shifted one bit to the left and the MSD of the input bit field is shifted to become the least significant digit (LSD).

Assignees

• IBM

Inventors

• Payer Stefan
• Klein Michael
• Lichtenau Cedric
• Richter Ralf

Classifications

• G01R31/318563

  Multiple simultaneous testing of subparts · CPC title

• G01R31/2834 Primary

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• G01R31/318558 Primary

  Addressing or selecting of subparts of the device under test · CPC title