Circuit and method for translation lookaside buffer (TLB) implementation
US-12541466-B1 · Feb 3, 2026 · US
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Ma Albert patents
Ma Albert is listed as an inventor on 20 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ma Albert |
| Total patents | 20 |
| First publication | May 19, 2016 |
| Latest publication | Feb 3, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
System and method for large memory transaction (LMT) stores
US-12282658-B1 · Apr 22, 2025 · US
Circuit and method for translation lookaside buffer (TLB) implementation
US-12032488-B1 · Jul 9, 2024 · US
System and method for large memory transaction (LMT) stores
US-11960727-B1 · Apr 16, 2024 · US
System and method for mapping memory addresses to locations in set-associative caches
US-11620225-B1 · Apr 4, 2023 · US
Configuration cache for the ARM SMMUv3
US-11474953-B2 · Oct 18, 2022 · US
System and method for mapping memory addresses to locations in set-associative caches
US-11416405-B1 · Aug 16, 2022 · US
Configuration Cache For The ARM SMMUv3
US-2020117613-A1 · Apr 16, 2020 · US
Instruction ordering for in-progress operations
US-10339054-B2 · Jul 2, 2019 · US
Sharing resources in a multi-context computing system
US-10303514-B2 · May 28, 2019 · US
Recent patents
Latest publications not already listed above.
Approach for interfacing a pipeline with two or more interfaces in a processor
US-10078601-B2 · Sep 18, 2018 · US
Instruction ordering for in-progress operations
US-2018165197-A1 · Jun 14, 2018 · US
Instruction ordering for in-progress operations
US-9910776-B2 · Mar 6, 2018 · US
Distributing resource requests in a computing system
US-9678717-B2 · Jun 13, 2017 · US
Caching TLB translations using a unified page table walker cache
US-9405702-B2 · Aug 2, 2016 · US
Distributing resource requests in a computing system
US-2016139883-A1 · May 19, 2016 · US
Instruction ordering for in-progress operations
US-2016140043-A1 · May 19, 2016 · US
Multiple memory management units
US-2016140059-A1 · May 19, 2016 · US
Caching tlb translations using a unified page table walker cache
US-2016140048-A1 · May 19, 2016 · US
Sharing resources in a multi-context computing system
US-2016139950-A1 · May 19, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Cavium Inc | 10 |
| Marvell Asia Pte Ltd | 7 |
| Cavium Llc | 2 |
| Marvell World Trade Ltd | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/1009 | 8 |
| G06F2212/1024 | 8 |
| G06F2212/657 | 5 |
| G06F12/0895 | 4 |
| G06F12/0808 | 4 |