Instruction ordering for in-progress operations

Patent metadata

Field	Value
Publication number	US-10339054-B2
Application number	US-201815890921-A
Country	US
Kind code	B2
Filing date	Feb 7, 2018
Priority date	Nov 14, 2014
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

First claim

What is claimed is:

1. An apparatus comprising:
one or more modules configured to execute memory instructions that access data stored in physical memory based on virtual addresses translated to physical addresses based on mappings in a page table; and
memory management circuitry coupled to the one or more modules, the memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses;
wherein the memory management circuitry is configured to execute operations from the one or more modules, the executing including selectively ordering each of a plurality of in-progress operations that were in progress within a processor pipeline when a first operation was received by the memory management circuitry,
wherein said selectively ordering is with respect to completing execution within said processor pipeline, and is performed in response to the first operation being received,
wherein the first operation invalidates at least a first virtual address as a result of inserting an instruction into the pipeline within a pre-determined maximum number of cycles after the first operation was received, wherein the pre-determined maximum number of cycles is determined based at least in part on (1) a guaranteed maximum latency and (2) a maximum number of cycles needed for the inserted instruction to propagate through the pipeline, and
wherein a position in said selective ordering of a particular in-progress operation depends on whether or not the particular in-progress operation provides results to at least one of the first cache or second cache.

2. The apparatus of claim 1 , wherein a position in said selective ordering of the particular in-progress operation is selected to be either: (1) before the first operation, or (2) after the first operation.

3. The apparatus of claim 2 , wherein execution of a set of operations by the memory management circuitry includes overlap in the execution of the first operation and the particular in-progress operation, but results of execution of the set of operations, with respect to their effect on other operations executed by the memory management circuitry, are provided atomically without overlap of any effects of results of the first operation and any effects of results of the particular in-progress operation.

4. The apparatus of claim 2 , wherein a first module of the one or more modules comprises a core configured as a central processing unit, and a second module of the one or more modules is configured for direct memory access without requiring the core.

5. The apparatus of claim 4 , wherein a position in said selective ordering of the particular in-progress operation is before the first operation if the particular in-progress operation was initiated by the second module.

6. The apparatus of claim 5 , wherein selecting the position of the particular in-progress operation to be before the first operation includes allowing the particular in-progress operation to continue execution concurrently with the first operation and preventing any results from the particular in-progress operation generated after the first operation was received by the memory management circuitry from being used to modify the first cache or second cache.

7. The apparatus of claim 5 , wherein the particular in-progress operation was initiated by the first module.

8. The apparatus of claim 7 , wherein the position of the particular in-progress operation is selected to be before the first operation if the particular in-progress operation does not provide results to the first cache and does not provide results to the second cache, and after the first operation if the particular in-progress operation does provide results to at least one of the first cache or the second cache.

9. The apparatus of claim 2 , wherein a position in said selective ordering of the particular in-progress operation depends on whether or not the in-progress operation provides results to at least one of the first cache or the second cache.

10. The apparatus of claim 9 , wherein the position of the particular in-progress operation is selected to be before the first operation if the particular in-progress operation does not provide results to the first cache and does not provide results to the second cache, and after the first operation if the particular in-progress operation does provide results to at least one of the first cache or the second cache.

11. The apparatus of claim 10 , wherein selecting the position of the particular in-progress operation to be before the first operation includes allowing the particular in-progress operation to continue execution concurrently with the first operation.

12. The apparatus of claim 10 , wherein selecting the position of the particular in-progress operation to be after the first operation includes aborting the particular in-progress operation and re-starting the particular in-progress operation after completing execution of the first operation.

13. The apparatus of claim 1 , wherein the first cache comprises a translation lookaside buffer that stores a subset consisting of fewer than all of the mappings in the page table.

14. The apparatus of claim 1 , wherein the second cache comprises a data cache that stores copies of data stored in the physical memory.

15. The apparatus of claim 1 , wherein the second cache comprises a page table walker cache that stores a limited number of intermediate results provided by a page table walker that traverses levels of a hierarchical page table having multiple levels that each store intermediate results for determining the mappings.

16. The apparatus of claim 1 , wherein the first operation comprises an operation that invalidates a range of virtual addresses that includes the first virtual address.

17. A method comprising:
executing memory instructions using one or more modules that access data stored in physical memory based on virtual addresses translated to physical addresses based on mappings in a page table; and
managing execution of the memory instructions using memory management circuitry coupled to the one or more modules, the memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses;
wherein the memory management circuitry executes operations from the one or more modules, the executing including selectively ordering each of a plurality of in-progress operations that were in progress within a processor pipeline when a first operation was received by the memory management circuitry,
wherein said selectively ordering is with respect to completing execution within said processor pipeline, and is performed in response to the first operation being received,
wherein the first operation invalidates at least a first virtual address as a result of inserting an instruction into the pipeline within a pre-determined maximum number of cycles after the first operation was received, wherein the pre-determined maximum number of cycles is determined based at least in part on (1) a guaranteed maximum latency and (2) a maximum number of cycles needed for the inserted instruction to propagate through the pipeline, and
wherein a position in said selective ordering of a particular in-progress operation depends on whether or not the particular in-progress operation provides results to at least one of the first cache or second cache.

18. The method of claim 17 , wherein a position in said selective ordering of the part

Assignees

• Cavium Llc

Inventors

• Mukherjee Shubhendu Sekhar
• Ma Albert
• Bertone Mike

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0808 Primary

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title