Caching TLB translations using a unified page table walker cache

Patent metadata

Field	Value
Publication number	US-9405702-B2
Application number	US-201414541616-A
Country	US
Kind code	B2
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A core executes memory instructions. A memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker. The MMU compares a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address, based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and removes any entries in the second cache that satisfy the match criterion.

First claim

What is claimed is:

1. An apparatus comprising:
a core configured to execute memory instructions that access data stored in physical memory based on virtual addresses translated to physical addresses based on a hierarchical page table having multiple levels that each store different intermediate results for determining final mappings between virtual addresses and physical addresses; and
a memory management unit (MMU) coupled to the core, the MMU including a first cache that stores a plurality of the final mappings of the page table, a page table walker that traverses the levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker;
wherein the MMU is configured to compare a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address;
wherein the comparison is based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache; and
wherein the MMU is configured to remove any entries in the second cache that satisfy the match criterion.

2. The apparatus of claim 1 , wherein the portion of an entry in the second cache that is compared with the portion of the first virtual address is a consecutive sequence of bits of a virtual address associated with an intermediate result stored in the entry.

3. The apparatus of claim 2 , wherein the comparison is based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and depends on a granule size of a page containing the virtual address associated with the intermediate result.

4. The apparatus of claim 2 , wherein the comparison comprises applying a bit mask to the entry in the second cache to determine the portion of the entry in the second cache, and applying a bit mask to the first virtual address to determine the portion of the first virtual address.

5. The apparatus of claim 4 , wherein the mask is computed in response to the request from the core to invalidate a first virtual address.

6. The apparatus of claim 4 , wherein the mask is stored in the entry in the second cache.

7. The apparatus of claim 1 , wherein the second cache includes entries that store intermediate results associated with multiple different levels of the page table.

8. The apparatus of claim 1 , wherein the first cache comprises a translation lookaside buffer that stores a subset consisting of fewer than all of the final mappings of the hierarchical page table.

9. The apparatus of claim 1 , further comprising a physical memory interface configured to access a first portion of the physical memory storing data referenced by physical addresses of a physical address space, and a second portion storing at least one level of the hierarchical page table.

10. The apparatus of claim 9 , further comprising a storage device storing data referenced by virtual addresses of a virtual address space.

11. The apparatus of claim 1 , wherein a first subset of the entries in the second cache are associated with a first level of the multiple levels of the of the hierarchical page table, a second subset of the entries in the second cache are associated with a second level of the multiple levels of the hierarchical page table, and the comparison of a portion of the first virtual address to the entries in the first subset is performed in parallel to the comparison of a portion of the first virtual address to the entries in the second subset.

12. The apparatus of claim 1 , wherein the comparison of a portion of the first virtual address to portions of entries in the second cache takes 3 processor cycles.

13. A method comprising:
executing, in a core, memory instructions that access data stored in physical memory based on virtual addresses translated to physical addresses based on a hierarchical page table having multiple levels that each store different intermediate results for determining final mappings between virtual addresses and physical addresses; and
managing, in a memory management unit (MMU) coupled to the core, a first cache that stores a plurality of the final mappings of the page table, a page table walker that traverses the levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker;
wherein the MMU compares a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address;
wherein the comparison is based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache; and
wherein the MMU removes any entries in the second cache that satisfy the match criterion.

14. The method of claim 13 , wherein the portion of an entry in the second cache that is compared with the portion of the first virtual address is a consecutive sequence of bits of a virtual address associated with an intermediate result stored in the entry.

15. The method of claim 14 , wherein the comparison is based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and depends on a granule size of a page containing the virtual address associated with the intermediate result.

16. The method of claim 14 , wherein the comparison comprises applying a bit mask to the entry in the second cache to determine the portion of the entry in the second cache, and applying a bit mask to the first virtual address to determine the portion of the first virtual address.

17. The method of claim 16 , wherein the mask is computed in response to the request from the core to invalidate a first virtual address.

18. The method of claim 16 , wherein the mask is stored in the entry in the second cache.

19. The method of claim 13 , wherein the second cache includes entries that store intermediate results associated with multiple different levels of the page table.

20. The method of claim 13 , wherein the first cache comprises a translation lookaside buffer that stores a subset consisting of fewer than all of the final mappings of the hierarchical page table.

21. The method of claim 13 , further comprising a physical memory interface configured to access a first portion of the physical memory storing data referenced by physical addresses of a physical address space, and a second portion storing at least one level of the hierarchical page table.

22. The method of claim 21 , further comprising a storage device storing data referenced by virtual addresses of a virtual address space.

23. The method of claim 13 , wherein a first subset of the entries in the second cache are associated with a first level of the multiple levels of the of the hierarchical page table, a second subset of the entries in the second cache are associated with a second level of the multiple levels of the hierarchical page table, and the comparison of a portion of the first virtual address to the entries in the first subset is performed in parallel to the comparison of a portion of the first virtual address to the entries in the second subset.

Assignees

• Cavium Inc

Inventors

• Mukherjee Shubhendu Sekhar
• Bertone Mike
• Ma Albert

Classifications

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F2212/683

  Invalidation · CPC title