Approach for interfacing a pipeline with two or more interfaces in a processor

Patent metadata

Field	Value
Publication number	US-10078601-B2
Application number	US-201514940982-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 14, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.

First claim

What is claimed is:

1. A method of interfacing a pipeline with two or more interfaces in a hardware processor, the method comprising:
providing a single pipeline in a hardware processor, the single pipeline presenting at least two visible units, the single pipeline including replicated architecturally visible structures belonging to each the visible units, shared logic resources shared among the replicated architecturally visible structures, and shared architecturally hidden structures shared among the visible units;
receiving a request from one of a plurality of interfaces at one of the at least two visible units;
tagging the request with an identifier based on the one of the at least two visible units that received the request; and
processing the request in the single pipeline by propagating the request through the replicated architecturally visible structures of a respective one of the visible units that corresponds with the identifier as directed by the shared logic resources.

2. The method of claim 1 , wherein the request is a memory request, and further comprising:
outputting a physical address to a memory to complete the memory request.

3. The method of claim 1 , wherein the architecturally visible structures include at least one of an architecturally visible memory, a content addressable memory, and a register, and the architecturally hidden structures include at least one of a transition look aside buffer and a page walker.

4. The method of claim 1 , wherein processing the request at the shared architecturally hidden structures includes receiving the request from any of the replicated architecturally visible structures.

5. The method of claim 1 , further comprising utilizing the architecturally hidden structures independent from utilizing of any of the replicated architecturally visible structures.

6. The method of claim 1 , further comprising:
converting information of the request representing at least one of a device, a user and a virtual machine to information representing a context including at least one of a virtual machine identifier, a process identifier, and at least one pointer to a page table.

7. The method of claim 1 , wherein each of the replicated architecturally visible structures corresponds with one of the presented visible units.

8. The method of claim 1 , wherein the visible units are arranged in parallel.

9. The method of claim 6 , wherein converting information of the request includes converting the information to a context at the replicated architecturally visible structures.

10. The method of claim 9 , further comprising converting the context to a physical memory address at the combined architecturally hidden structures.

11. A system for interfacing a pipeline with two or more interfaces in a hardware processor, the system comprising:
a single pipeline in a hardware processor, the single pipeline presenting at least two visible units, the single pipeline including replicated architecturally visible structures belonging to each of the visible units, shared logic resources shared among the replicated architecturally visible structures, and shared architecturally hidden structures shared among the visible units, wherein the at least two visible units are configured to receive a request from one of a plurality of interfaces; and
a tagging module configured to tag the request with an identifier based on the one of the at least two visible units that received the request; and
wherein the single pipeline is configured to process the request by propagating the request through the replicated architecturally visible structures of a respective one of the visible units that corresponding with the identifier as directed by the shared logic resources.

12. The system of claim 11 , wherein:
the request is a memory request, and
the single pipeline is further configured to output a physical address to a memory to complete the memory request.

13. The method of claim 11 , wherein the architecturally visible structures include at least one of an architecturally visible memory, a content addressable memory, and a register, and the architecturally hidden structures include at least one of a transition look aside buffer and a page walker.

14. The system of claim 11 , wherein the architecturally hidden structures are further configured to process the request by receiving the request from any of the replicated architecturally visible structures.

15. The system of claim 11 , wherein the architecturally hidden structures are utilized independently from utilizing of any of the replicated architecturally visible structures.

16. The system of claim 11 , wherein the single pipeline is configured to convert information of the request representing at least one of a device, a user and a virtual machine to information representing a context including at least one of a virtual machine identifier, a process identifier, and at least one pointer to a page table.

17. The system of claim 11 , wherein each of the replicated architecturally visible units corresponds with one of the presented visible units.

18. The method of claim 11 , wherein the visible units are arranged in parallel.

19. The system of claim 16 , wherein the single pipeline is further configured to convert information of the request at the replicated architecturally visible structures.

20. The system of claim 19 , wherein the single pipeline is further configured to convert the context to a physical memory address at the architecturally hidden structures.

Assignees

• Cavium Inc

Inventors

• Snyder Ii Wilson P
• Kujtkowski Anna
• Ma Albert
• Scrobohaci Paul G

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/1605 Primary

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title