Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory

Patent metadata

Field	Value
Publication number	US-10198354-B2
Application number	US-201715465513-A
Country	US
Kind code	B2
Filing date	Mar 21, 2017
Priority date	Mar 21, 2017
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

First claim

What is claimed:

1. An apparatus in communication with a first memory, a second memory, a processor, and a power control unit, comprising:
a first memory controller coupled to the first memory and including at least one Reliability, Availability, and Serviceability (RAS) controller, wherein each RAS controller reads a range of addresses in the first memory; and
a second memory controller coupled to the second memory comprising a non-volatile memory;
wherein the first memory controller and the second memory controller operate to:
in response to the first memory controller receiving a command from the power control unit, invoke the at least one RAS controller to read data from at least one range of addresses specified for the RAS controller from the first memory;
determine, by the second memory controller, whether the data read from the first memory comprises modified data;
transfer, by the second memory controller, the data read from the first memory determined to be modified to the second memory; and
send, by the first memory controller, a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading data in the range of addresses.

2. The apparatus of claim 1 , wherein the second memory controller is further to discard the data read from the first memory by the RAS controller that does not comprise modified data without transferring to the second memory.

3. The apparatus of claim 1 coupled to a battery, wherein the battery supplies power to the first memory controller and the second memory controller while the at least one RAS controller reads data from the range of addresses until the RAS controller has read all the data from the range of addresses and the second memory controller has transferred modified data read by the at least one RAS controller to the second memory.

4. The apparatus of claim 1 , wherein the first memory is comprised of a plurality of memory dies, wherein the at least one RAS controller comprises a plurality of RAS controllers each associated with a range of addresses in at least one memory channel to at least one of the memory dies, wherein each of the RAS controllers receives the command and in response reads data at the range of addresses of the RAS controller, and wherein each of the RAS controllers sends a signal to notify the power control unit that the modified data in the range of addresses for the RAS controller was flushed in response to reading data in all of the range of addresses.

5. The apparatus of claim 1 , wherein the at least one RAS controller is configured with the range of addresses specified for the RAS controller from initialization firmware during initialization.

6. The apparatus of claim 1 , wherein in response to the command, the first memory controller drains pending write data in a buffer to the first memory, and wherein the at least one RAS controller reads data from the range of addresses in response to the first memory controller draining the pending write data to the first memory.

7. The apparatus of claim 1 , wherein the power control unit initiates a power down operation for the processor in response to receiving a signal from each of the at least one RAS controller indicating that any modified data at the range of addresses specified for the RAS controller was read.

8. The apparatus of claim 1 , wherein the at least one RAS controller is further to:
operate in a normal operation mode, prior to receiving the command from the power control unit, to continuously read data at each of the at least one range of addresses specified for the RAS controller to perform error correction on the read data and write back to the first memory; and
terminate the normal operation mode for the command.

9. The apparatus of claim 1 , wherein the first memory provides a cache to the second memory, wherein during a normal operation mode, the second memory controller receives direct memory requests to requested data in the second memory and determines whether the requested data is cached in the first memory, wherein read requested data in the first memory is returned from the first memory and wherein in response to a write request, write data is written to the first memory.

10. The apparatus of claim 1 , wherein the first memory comprises a dynamic random access memory (DRAM) and wherein the second memory comprises a non-volatile memory device.

11. A system, comprising:
a processor;
a first memory;
a second memory comprising a non-volatile memory;
a first memory controller coupled to the first memory and including at least one RAS controller, wherein each RAS controller reads a range of addresses in the first memory;
a second memory controller coupled to the second memory; and
a power control unit to supply power to the processor, the first memory, the second memory, the first memory controller, and the second memory controller,
wherein the first memory controller and the second memory controller operate to:
in response to the first memory controller receiving a command from the power control unit, invoke the at least one RAS controller to read data from at least one range of addresses specified for the RAS controller from the first memory;
determine, by the second memory controller, whether the data read from the first memory comprises modified data;
transfer, by the second memory controller, the data read from the first memory determined to be modified to the second memory; and
send, by the first memory controller, a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading data in the range of addresses.

12. The system of claim 11 , further comprising:
a battery to supply power to the first memory controller and the second memory controller while the at least one RAS controller reads data from the range of addresses until the RAS controller has read all the data from the range of addresses and the second memory controller has transferred modified data read by the at least one RAS controller to the second memory.

13. The system of claim 11 , wherein the first memory is comprised of a plurality of memory dies, wherein the at least one RAS controller comprises a plurality of RAS controllers each associated with a range of addresses in at least one memory channel to at least one of the memory dies, wherein each of the RAS controllers receives the command and in response reads data at the range of addresses of the RAS controller, and wherein each of the RAS controllers sends a signal to notify the power control unit that the modified data in the range of addresses for the RAS controller was flushed in response to reading data in all of the range of addresses.

14. The system of claim 11 , further comprising:
initialization firmware to configure the at least one RAS controller with the range of addresses specified for the RAS controller from during system initialization.

15. The system of claim 11 , wherein in response to the command, the first memory controller drains pending write data from a buffer to the first memory, and wherein the at least one RAS controller reads data from the range of addresses in response to the first memory controller draining the pending write data to the first memory.

16. The system of claim 11 , wherein the power control unit initiates a power down operation for the processor in response to receiving a signal from eac

Assignees

• Intel Corp

Inventors

• Chen Wei
• Agarwal Rajat
• Ling Jing
• Liu Daniel W

Classifications

• G06F12/0808 Primary

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title