Boot process with parallel memory initialization

Patent metadata

Field	Value
Publication number	US-10346177-B2
Application number	US-201615378878-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Dec 14, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

An embodiment of a memory apparatus may include a system memory, and a memory manager communicatively coupled to the system memory to determine a first amount of system memory needed for a boot process, initialize the first amount of system memory, start the boot process, and initialize additional system memory in parallel with the boot process. Other embodiments are disclosed and claimed.

First claim

We claim:

1. An electronic processing system, comprising:
a processor;
a persistent storage media communicatively coupled to the processor to store a basic input/output system (BIOS) and an operating system (OS);
a system memory communicatively coupled to the processor;
a patrol engine communicatively coupled to the system memory to patrol scrub the system memory; and
a memory manager communicatively coupled to the system memory to:
retrieve a first parameter which corresponds to a first amount of the system memory needed for a BIOS load process,
initialize the first amount of the system memory in accordance with the retrieved first parameter,
start the BIOS load process,
initialize an additional amount of the system memory in parallel with the BIOS load process, and
allocate more than one write credit to the patrol engine.

2. The electronic processing system of claim 1 , wherein the memory manager is further to:
retrieve a second parameter which corresponds to an amount of write credits to allocate to the patrol engine, wherein the amount of the write credits to allocate to the patrol engine is more than fifty percent of the write credits; and
allocate the amount of the write credits to the patrol engine in accordance with the retrieved second parameter,
and wherein the patrol engine is to write full cache lines of zeros to the system memory without reading the system memory.

3. The electronic processing system of claim 1 , wherein the memory manager is further to:
retrieve a third parameter which corresponds to a second amount of the system memory needed for an OS load process after the BIOS load process;
initialize the second amount of the system memory in accordance with the retrieved third parameter;
start the OS load process; and
initialize an additional amount of the system memory in parallel with the OS load process.

4. A memory apparatus, comprising:
a system memory;
a patrol engine communicatively coupled to the system memory to patrol scrub the system memory; and
a memory manager communicatively coupled to the system memory to:
determine a first amount of the system memory needed for a boot process,
initialize the first amount of the system memory,
start the boot process,
initialize an additional amount of the system memory in parallel with the boot process, and
allocate more than one write credit to the patrol engine.

5. The memory apparatus of claim 4 , wherein the patrol engine is further to write full cache lines of zeros to the system memory without reading the system memory.

6. The memory apparatus of claim 4 , wherein the memory manager is further to allocate more than fifty percent of write credits to the patrol engine.

7. The memory apparatus of claim 4 , wherein the memory manager is further to:
retrieve a first parameter which corresponds to an amount of the system memory needed for the boot process;
determine the first amount of the system memory in accordance with the retrieved first parameter;
retrieve a second parameter which corresponds to an amount of write credits to allocate to the patrol engine; and
allocate the amount of the write credits to the patrol engine in accordance with the retrieved second parameter.

8. The memory apparatus of claim 4 , wherein the memory manager is further to:
determine a second amount of the system memory needed for an operating system load process after the boot process;
initialize the second amount of the system memory;
start the operating system load process; and
initialize an additional amount of the system memory in parallel with the operating system load process.

9. A method of managing memory, comprising:
determining a first amount of a memory needed for a boot process;
initializing the first amount of the memory;
starting the boot process;
initializing an additional amount of the memory in parallel with the boot process;
patrol scrubbing the memory; and
allocating more than one write credit to the patrol scrubbing.

10. The method of claim 9 , wherein any of the initializing comprises:
the patrol scrubbing the memory.

11. The method of claim 10 , wherein the patrol scrubbing the memory comprises:
writing full cache lines of zeros to the memory without reading the memory.

12. The method of claim 10 , further comprising:
retrieving a first parameter corresponding to an amount of the memory needed for the boot process;
determining the first amount of the memory in accordance with the retrieved first parameter;
retrieving a second parameter corresponding to an amount of write credits to allocate to the patrol scrubbing; and
allocating the amount of the write credits to the patrol scrubbing in accordance with the retrieved second parameter.

13. The method of claim 9 , further comprising:
allocating more than fifty percent of write credits to the patrol scrubbing.

14. The method of claim 9 , further comprising:
determining a second amount of the memory needed for an operating system load process after the boot process;
initializing the second amount of the memory;
starting the operating system load process; and
initializing an additional amount of the memory in parallel with the operating system load process.

15. At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
determine a first amount of a memory needed for a boot process;
initialize the first amount of the memory;
start the boot process;
initialize an additional amount of the memory in parallel with the boot process;
patrol scrub the memory; and
allocate more than one write credit to patrol scrub the memory.

16. The at least one non-transitory computer readable medium of claim 15 , comprising a further set of instructions, which when executed by a computing device, cause the computing device to:
write full cache lines of zeros to the memory without reading the memory.

17. The at least one non-transitory computer readable medium of claim 15 , comprising a further set of instructions, which when executed by a computing device, cause the computing device to:
allocate more than fifty percent of write credits to patrol scrub the memory.

18. The at least one non-transitory computer readable medium of claim 15 , comprising a further set of instructions, which when executed by a computing device, cause the computing device to:
retrieve a first parameter corresponding to an amount of the memory needed for the boot process;
determine the first amount of the memory in accordance with the retrieved first parameter;
retrieve a second parameter corresponding to an amount of write credits to allocate to patrol scrub the memory; and
allocate the amount of the write credits to patrol scrub the memory in accordance with the retrieved second parameter.

19. The at least one non-transitory computer readable medium of claim 15 , comprising a further set of instructions, which when executed by a computing device, cause the computing device to:
determine a second amount of the memory needed for an operating system load process after the boot process;
initialize the second amount of the memory;
start the operating system load process; and
initialize an additional amount of the memory in parallel with the operating system load process.

Assignees

• Intel Corp

Inventors

• Natu Mahesh S
• Chen Wei
• Ling Jing
• Mccormick Jr James E

Classifications

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F9/4406 Primary

  Loading of operating system · CPC title