Built-in self test circuit for segmented static random access memory (sram) array input/output

Patent metadata

Field	Value
Publication number	US-2024069096-A1
Application number	US-202318228048-A
Country	US
Kind code	A1
Filing date	Jul 31, 2023
Priority date	Aug 30, 2022
Publication date	Feb 29, 2024
Grant date	—

Abstract

An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.

First claim

What is claimed is:

1 . A memory circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column; a word line drive circuit for each row having an output connected to drive the word line of the row; a row decoder circuit configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory read and a second mode where the row decoder circuit simultaneously actuates one word line per sub-array during the memory read; an input/output circuit for each column comprising:
a plurality of bit line inputs coupled to the local bit lines of the sub-arrays;
a column data output coupled to the plurality of bit line inputs; and
a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding bit line input; and
a built-in self test (BIST) circuit configured to perform BIST testing of the memory circuit dependent on data generated at the column data output and perform BIST testing of the memory circuit dependent on data generated at the plurality of sub-array data outputs.

2 . The circuit of claim 1 , wherein the BIST circuit comprises:
a multiplexing circuit having inputs coupled to the plurality of sub-array data outputs and a selection input configured to receive a selection signal; a comparison circuit having a first input coupled to receive an output of the multiplexing circuit and a second input coupled to the column data output; and a BIST control circuit configured to generate the selection signal to cause the multiplexing circuit to select data from one of the plurality of sub-array data outputs for comparison by said comparison circuit to data at the column data output.

3 . The circuit of claim 2 , wherein said BIST control circuit is configured to apply test data to the memory cells of the memory array and further configured to process data generated at the column data output in response to the test data to test the memory circuit for operation in the first mode of memory circuit operation and process data generated at an output of the comparison circuit in response to the test data to test the memory circuit for operation in the second mode of memory circuit operation.

4 . The circuit of claim 1 , wherein the BIST circuit comprises:
a multiplexing circuit having inputs coupled to the plurality of sub-array data outputs and a selection input configured to receive a selection signal; a comparison circuit having a first input coupled to receive a read data signal output of the multiplexing circuit and a second input coupled to receive a write data signal; and a BIST control circuit configured to generate test data for application to the memory circuit, said test data including said write data signal, and configured to generate the selection signal to cause the multiplexing circuit to select said read data signal from one of the plurality of sub-array data outputs for comparison by said comparison circuit to said write data signal.

5 . The circuit of claim 4 , wherein said comparison circuit comprises a logical XOR circuit.

6 . The circuit of claim 4 , wherein data at the column data output is dependent on the write data signal of said test data.

7 . The circuit of claim 4 , wherein the BIST circuit is configured to process data generated at the column data output in response to the test data to test the memory circuit for operation in the first mode of memory circuit operation and process data generated at an output of the comparison circuit in response to the test data to test the memory circuit for operation in the second mode of memory circuit operation.

8 . The circuit of claim 1 , further comprising:
a multiplexing circuit having inputs coupled to the plurality of sub-array data outputs and a selection input configured to receive a selection signal; and a comparison circuit having a first input coupled to receive a read data signal output of the multiplexing circuit and a second input coupled to the column data output; wherein said BIST circuit is configured to perform BIST testing of the memory circuit when in the second mode of memory circuit operation dependent on a flag signal generated at an output of the comparison circuit.

9 . The circuit of claim 8 , wherein said multiplexing circuit and comparison circuit are components in each input/output circuit and the flag signal is an output of each input/output circuit.

10 . The circuit of claim 8 , wherein said selection signal is generated by the row decoder circuit dependent on word line actuation and mode of memory circuit operation.

11 . The circuit of claim 8 , wherein said BIST circuit is configured to apply test data to the memory cells of the memory array and further configured to process data generated at the column data output in response to the test data to test the memory circuit for operation in the first mode of memory circuit operation and process the flag signal in response to the test data to test the memory circuit for operation in the second mode of memory circuit operation.

12 . The circuit of claim 1 , wherein each input/output circuit further comprises:
a first multiplexing circuit having inputs coupled to the plurality of bit line inputs and a selection input configured to receive a selection signal; a second multiplexing circuit having inputs coupled to the plurality of sub-array data outputs and a selection input configured to receive said selection signal; and a third multiplexing circuit having inputs coupled to outputs of the first and second multiplexing circuits and a selection input configured to receive a control signal; wherein said column data output coupled to an output of the third multiplexing circuit; and wherein said BIST circuit is configured to apply a first logic state for the control signal and perform BIST testing of the memory circuit dependent on data generated at the column data output from data at the plurality of bit line inputs and configured to apply a second logic state for the control signal and perform BIST testing of the memory circuit dependent on data generated at the column data output from data at the plurality of sub-array data outputs.

13 . The circuit of claim 12 , wherein said selection signal is generated by the row decoder circuit dependent on word line actuation and mode of memory circuit operation.

14 . The circuit of claim 12 , wherein said BIST circuit is configured to apply test data to the memory cells of the memory array and further configured to process data generated at the output of the first multiplexing circuit in response to the test data to test the memory circuit for operation in the first mode of memory circuit operation and process data generated at the output of the second multiplexing circuit in response to the test data to test the memory circuit for operation in the second mode of memory circuit operation.

15 . A memory circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column; a word line drive circuit for each row having an output connected to driv

Assignees

• St Microelectronics Int Nv

Inventors

• Singh Bhupender
• Chawla Hitesh
• Kumar Tanuj
• Rawat Harsh
• Dhori Kedar Janardan
• Ayodhyawasi Manuj
• Chawla Nitin
• Kumar Promod

Classifications

• G11C2029/1204

  Bit line control · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G01R31/31724 Primary

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title