Handling interrupts from a virtual function in a system with a reconfigurable processor

Patent metadata

Field	Value
Publication number	US-12340195-B2
Application number	US-202318118428-A
Country	US
Kind code	B2
Filing date	Mar 7, 2023
Priority date	Feb 2, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A system is presented that includes a communication link, a runtime processor coupled to the communication link, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes multiple arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the physical function driver and to a virtual function driver of the at least one virtual function driver within the runtime processor.

First claim

What is claimed is:

1. A system, comprising:
a communication link;
a runtime processor that is operatively coupled to the communication link; and
a reconfigurable processor adapted for generating an interrupt to the runtime processor in response to a predetermined event, the reconfigurable processor comprising:
multiple arrays of coarse-grained reconfigurable units, and
an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link,
wherein the runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, wherein each one of at least one virtual function is associated with a corresponding one of the at least one virtual function driver, wherein a first virtual function of the at least one virtual function that is associated with a first virtual function driver of the at least one virtual function driver has exclusive access among the at least one virtual function to a predetermined array of the multiple arrays of coarse-grained reconfigurable units, and wherein the reconfigurable processor is adapted for only notifying the physical function driver and the first virtual function driver within the runtime processor about the interrupt when the predetermined event occurred in the predetermined array of the multiple arrays of coarse-grained reconfigurable units.

2. The system of claim 1 , wherein a physical function that is associated with the physical function driver has exclusive access to a first portion of the multiple arrays of coarse-grained reconfigurable units, and wherein the physical function shares access to a second portion of the multiple arrays of coarse-grained reconfigurable units that is different than the first portion with the first virtual function.

3. The system of claim 2 , wherein each virtual function of the at least one virtual function has exclusive access among the at least one virtual function to at least one array of the multiple arrays of coarse-grained reconfigurable units.

4. The system of claim 1 , wherein the predetermined event comprises at least one of a load-complete event, an execution-complete event, a checkpoint event, a direct memory access (DMA) completion event, a DMA error event, a memory access error, or a runtime exception.

5. The system of claim 1 , wherein the reconfigurable processor further comprises:
storage circuitry that is adapted for storing a first identifier that identifies an array of the multiple arrays of coarse-grained reconfigurable units that generated the interrupt and for storing a second identifier that identifies the predetermined event that caused the interrupt.

6. The system of claim 5 , wherein the communication link comprises a Peripheral Component Interface Express (PCIe) bus and the reconfigurable processor is adapted for implementing a PCIe message signaled interrupt (MSI-X) in response to the predetermined event.

7. The system of claim 6 , wherein the storage circuitry further comprises:
status registers that are adapted for storing the first identifier; and
an interrupt status array (ISA) that is adapted for storing the second identifier.

8. The system of claim 7 , wherein the reconfigurable processor is adapted for implementing a pair of ISA and status registers for the physical function and another pair of ISA and status registers for each one of the at least one virtual function.

9. The system of claim 1 , further comprising:
external memory that is operatively coupled to the communication link, wherein the first virtual function has exclusive access among the at least one virtual function to a predetermined portion of the external memory, and wherein the reconfigurable processor is adapted for only notifying the physical function driver and the first virtual function driver about the interrupt when the predetermined event occurred in the predetermined portion of the external memory or during access to the predetermined portion of the external memory.

10. The system of claim 1 , wherein the reconfigurable processor further comprises:
a virtualization mailbox for sending messages from the physical function to the first virtual function, wherein the physical function generates an additional interrupt when the physical function sends a message to the first virtual function, and wherein the reconfigurable processor is adapted for only notifying the first virtual function about the additional interrupt.

11. A method of operating a system that comprises a communication link, a runtime processor that is operatively coupled to the communication link, and a reconfigurable processor comprising multiple arrays of coarse-grained reconfigurable units, and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link, comprising:
configuring, with the runtime processor, the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, wherein a first virtual function of at least one virtual function is associated with a first virtual function driver of the at least one virtual function driver;
providing, with the runtime processor, the first virtual function with exclusive access among the at least one virtual function to a predetermined array of the multiple arrays of coarse-grained reconfigurable units;
generating, with the reconfigurable processor, an interrupt in response to a predetermined event; and
reporting, with the reconfigurable processor, the interrupt to the physical function driver in the runtime processor and to the first virtual function driver in the runtime processor when the predetermined event occurred in the predetermined array of the multiple arrays of coarse-grained reconfigurable units.

12. The method of claim 11 , wherein the reconfigurable processor further comprises storage circuitry, further comprising:
storing a first identifier in the storage circuitry that identifies an array of the multiple arrays of coarse-grained reconfigurable units that generated the interrupt; and
storing a second identifier in the storage circuitry that identifies the predetermined event that caused the interrupt.

13. The method of claim 11 , wherein the communication link comprises a Peripheral Component Interface Express (PCIe) bus, further comprising:
with the reconfigurable processor, implementing a PCIe message signaled interrupt (MSI-X) in response to the predetermined event.

14. The method of claim 11 , wherein the system further comprises external memory that is operatively coupled to the communication link, and wherein the first virtual function has exclusive access among the at least one virtual function to a predetermined portion of the external memory, further comprising:
with the reconfigurable processor, only notifying the physical function driver and the first virtual function driver about the interrupt when the predetermined event occurred in the predetermined portion of the external memory or during access to the predetermined portion of the external memory.

15. The method of claim 11 , wherein the reconfigurable processor further comprises a virtualization mailbox for sending messages from a physical function that is associated with the physical function driver to the first virtual function, and wherein the physical function generates an additional interrupt when the physi

Assignees

• Sambanova Systems Inc

Inventors

• Shah Manish K
• Jordan Paul
• Wilson Maran
• Kumar Ravinder

Classifications

• G06F2009/45595

  Network integration; Enabling network access in virtual machine instances · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title