Handling interrupts from a virtual function in a system with a Multi-Die reconfigurable processor

Patent metadata

Field	Value
Publication number	US-12554473-B2
Application number	US-202318118410-A
Country	US
Kind code	B2
Filing date	Mar 7, 2023
Priority date	Feb 2, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A system is presented that includes a communication link, a runtime processor, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes first and second dies arranged in a package, having respective first and second arrays of coarse-grained reconfigurable (CGR) units, and respective first and second communication link interfaces coupled to the communication link. The runtime processor is adapted for configuring the first and second communication link interfaces to provide access to the first and second arrays of coarse-grained reconfigurable units from first and second physical function drivers and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the first or to the second physical function driver and for sending the interrupt to a virtual function driver of the at least one virtual function driver.

First claim

What is claimed is:

1 . A system, comprising:
a communication link; a runtime processor that is operatively coupled to the communication link; a reconfigurable processor adapted for generating an interrupt to the runtime processor in response to a predetermined event, the reconfigurable processor comprising:
a package;
a first die that is arranged in the package and comprises:
first arrays of coarse-grained reconfigurable units,
and a first communication link interface that couples the first die to the runtime processor via the communication link; and

a second die that is arranged in the package and comprises:
second arrays of coarse-grained reconfigurable units, and
a second communication link interface that couples the second die to the runtime processor via the communication link,

wherein the runtime processor is adapted for configuring the first and second communication link interfaces to provide access to the first and second arrays of coarse-grained reconfigurable units from first and second physical function drivers and from at least one virtual function driver, and wherein the reconfigurable processor is adapted for sending the interrupt to the first physical function driver or for sending the interrupt to the second physical function driver and for sending the interrupt to a virtual function driver of the at least one virtual function driver.

2 . The system of claim 1 , wherein each virtual function of at least one virtual function associated with the at least one virtual function driver has exclusive access among the at least one virtual function to at least one array of the first arrays of coarse-grained reconfigurable units or to at least one array of the second arrays of coarse-grained reconfigurable units.

3 . The system of claim 1 , wherein the predetermined event comprises at least one of a load-complete event, an execution-complete event, a checkpoint event, a direct memory access (DMA) completion event, a DMA error event, a memory access error, or a runtime exception.

4 . The system of claim 1 , wherein each one of the first and second dies of the reconfigurable processor further comprises:
storage circuitry that is adapted for storing a first identifier that identifies an array of the first and second arrays of coarse-grained reconfigurable units that generated the interrupt and for storing a second identifier that identifies the predetermined event that caused the interrupt.

5 . The system of claim 4 , wherein the communication link comprises a Peripheral Component Interface Express (PCIe) bus and the first and second communication link interfaces comprise respective PCIe interfaces, wherein the reconfigurable processor is adapted for sending a first PCIe message signaled interrupt (MSI-X) to the runtime processor in response to the predetermined event occurring on the first die, and wherein the reconfigurable processor is adapted for sending a second PCIe message signaled interrupt (MSI-X) to the runtime processor in response to the predetermined event occurring on the second die.

6 . The system of claim 5 , wherein the storage circuitry further comprises:
status registers that are adapted for storing the first identifier; and an interrupt status array (ISA) that is adapted for storing the second identifier.

7 . The system of claim 6 , wherein the runtime processor is adapted for implementing a pair of ISA and status registers for each one of the first and second physical function drivers and for each one of the at least one virtual function driver.

8 . The system of claim 1 , wherein a first virtual function of at least one virtual function that is associated with the at least one virtual function driver has exclusive access among the at least one virtual function to a predetermined array of the first arrays of coarse-grained reconfigurable units, and wherein the reconfigurable processor is adapted for routing the interrupt to the first physical function driver and to a first virtual function driver that is associated with the first virtual function when the predetermined event occurred in the predetermined array of the first arrays of coarse-grained reconfigurable units.

9 . The system of claim 8 , further comprising:
external memory that is operatively coupled to the communication link, wherein the first virtual function has exclusive access among the at least one virtual function to a predetermined portion of the external memory, and wherein the reconfigurable processor is adapted for routing the interrupt to the first physical function driver and to the first virtual function driver when the predetermined event occurred in the predetermined portion of the external memory or during access to the predetermined portion of the external memory.

10 . The system of claim 8 , wherein the reconfigurable processor further comprises:
a virtualization mailbox for sending messages from a first physical function that is associated with the first physical function driver to the first virtual function, wherein the first physical function generates an additional interrupt when the first physical function sends a message to the first virtual function, and wherein the reconfigurable processor is adapted for routing the additional interrupt to the first virtual function driver.

11 . A method of operating a system that comprises a communication link, a runtime processor that is operatively coupled to the communication link, and a reconfigurable processor comprising a package, first and second dies that are arranged in the package, wherein the first die comprises first arrays of coarse-grained reconfigurable units and a first communication link interface that couples the first die to the runtime processor via the communication link, and wherein the second die comprises second arrays of coarse-grained reconfigurable units and a second communication link interface that couples the second die to the runtime processor via the communication link, the method comprising:
configuring, with the runtime processor, the first and second communication link interfaces to provide access to the first and second arrays of coarse-grained reconfigurable units from first and second physical function drivers and from at least one virtual function driver; generating, with the reconfigurable processor, an interrupt in response to a predetermined event; and routing, with the reconfigurable processor, the interrupt to one of the first physical function driver or the second physical function driver and to a virtual function driver of the at least one virtual function driver.

12 . The method of claim 11 , wherein each die of the first and second dies of the reconfigurable processor further comprises storage circuitry, the method further comprising:
storing a first identifier in the storage circuitry that identifies an array of the first and second arrays of coarse-grained reconfigurable units that generated the interrupt; and storing a second identifier in the storage circuitry that identifies the predetermined event that caused the interrupt.

13 . The method of claim 12 , wherein the communication link comprises a Peripheral Component Interface Express (PCIe) bus, the method further comprising:
with the reconfigurable processor, implementing a PCIe message signaled interrupt (MSI-X) in response to the predetermined event.

14 . The method of claim 13 , wherein the storage circuitry further comprises status registers that are adapted for storing the first identifier and an interrupt status array (ISA) that is adapted for storing the second identifier, the method further comprising:
with the reconfigurable pro

Assignees

• Sambanova Systems Inc

Inventors

• Shah Manish K
• Jordan Paul
• Wilson Maran
• Kumar Ravinder

Classifications

• G06F2009/45595

  Network integration; Enabling network access in virtual machine instances · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title