Data processing system with link-based resource allocation for reconfigurable processors

Patent metadata

Field	Value
Publication number	US-12413530-B2
Application number	US-202418740240-A
Country	US
Kind code	B2
Filing date	Jun 11, 2024
Priority date	Mar 26, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

The disclosed technology relates to link-based resource allocation for a pool of reconfigurable processors. Resource allocation is provided for reconfigurable processors based on link bandwidths and link latencies. Runtime logic receives target link bandwidth and target link latency and rated link bandwidth and rated link latency. In response, the runtime logic allocates configuration files for an application, reconfigurable processors, and links between the processors. The runtime logic executes the allocated configuration files using the allocated processors and the allocated links. In another embodiment, the pool of reconfigurable processors comprise a cluster of processing nodes connected through a network.

First claim

What is claimed is:

1. A data processing system, comprising:
a pool of reconfigurable processors operatively coupled by links, the links having rated link bandwidths and rated link latencies;
runtime logic operatively coupled to the pool of reconfigurable processors, the runtime logic configured to receive, for a first application, a first plurality of configuration files containing configuration data;
a first configuration of a first plurality of virtual reconfigurable processors required to execute the first application;
virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors; and
a first specification of target link bandwidths and target link latencies of the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors;
using the runtime logic to allocate the reconfigurable processors in the plurality of reconfigurable processors to the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors;
using the runtime logic to allocate links between the reconfigurable processors to the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors based on a link bandwidth comparison that compares the target link bandwidths, specified by the first specification, against the rated link bandwidths, and a link latency comparison that compares the target link latencies, specified by the first specification, against the rated link latencies; and
using the runtime logic to allocate the reconfigurable processors and the links with configuration data in the first plurality of configuration files, forming configured reconfigurable processors and configured links; and
executing the first application using the configured reconfigurable processors and the configured links.

2. The data processing system of claim 1 , wherein the runtime logic is further configured to receive, for a second application, a second plurality of configuration files that contain configuration data;
a second configuration of a second plurality of virtual reconfigurable processors required to execute the second application;
virtual links between virtual reconfigurable processors in the second plurality of virtual reconfigurable processors; and
a second specification of target link bandwidths and target link latencies of the virtual links between the virtual reconfigurable processors in the second plurality of virtual reconfigurable processors.

3. The data processing system of claim 1 , wherein the pool of reconfigurable processors comprise a cluster of processing nodes connected through a network.

4. The data processing system of claim 1 , wherein one or more reconfigurable processors are host processors for controlling dataflow through a network.

5. The data processing system of claim 3 , wherein the pool of reconfigurable processors is associated with a single processing node in a network.

6. The data processing system of claim 3 , wherein the pool of reconfigurable processors is associated with multiple processing nodes in a network.

7. The data processing system of claim 3 , where the allocated reconfigurable processors are on a same processing node.

8. The data processing system of claim 3 , where the allocated reconfigurable processors are on a different processing node.

9. The data processing system of claim 1 , wherein the pool of reconfigurable processors is dynamically scalable to meet the performance requirements of applications requesting execution.

10. The system of claim 1 , wherein the processor elements are respective arrays of configurable units.

11. The system of claim 5 , wherein the reconfigurable processors are pattern compute units (PCUs) and pattern memory units (PMUs).

12. A computer-implemented method, comprising:
providing a pool of reconfigurable processors operatively coupled by links, the links having rated link bandwidths and rated link latencies;
providing runtime logic operatively coupled to the pool of reconfigurable processors, the runtime logic configured to receive, for a first application, a first plurality of configuration files containing configuration data;
providing a first configuration of a first plurality of virtual reconfigurable processors required to execute the first application;
providing virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors; and
providing a first specification of target link bandwidths and target link latencies of the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors;
using the runtime logic, allocating reconfigurable processors in the plurality of reconfigurable processors to the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors;
using the runtime logic, allocating links between the reconfigurable processors to the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors based on a link bandwidth comparison that compares the target link bandwidths, specified by the first specification, against the rated link bandwidths, and a link latency comparison that compares the target link latencies, specified by the first specification, against the rated link latencies;
using the runtime logic, allocating the reconfigurable processors and the links with configuration data in the first plurality of configuration files, forming configured reconfigurable processors and configured links; and
executing the first application using the configured reconfigurable processors and the configured links.

13. The computer-implemented method of claim 12 , wherein the runtime logic is further configured to receive, for a second application, a second plurality of configuration files that contain configuration data;
a second configuration of a second plurality of virtual reconfigurable processors required to execute the second application;
virtual links between virtual reconfigurable processors in the second plurality of virtual reconfigurable processors; and
a second specification of target link bandwidths and target link latencies of the virtual links between the virtual reconfigurable processors in the second plurality of virtual reconfigurable processors.

14. The computer-implemented method of claim 12 , wherein the bandwidth and latency are achievable bandwidth and achievable latency.

15. The computer-implemented method of claim 12 , wherein the pool of reconfigurable processors comprise a cluster of processing nodes connected through a network.

16. The computer-implemented method of claim 12 , wherein one or more reconfigurable processors are host processors for controlling dataflow through a network.

17. The computer-implemented method of claim 15 , wherein the pool of reconfigurable processors is a single processing node or multiple processing nodes coupled to a plurality of reconfigurable processors.

18. The computer-implemented method of claim 15 , wherein the allocated reconfigurable processors are on a same processing node.

19. The computer-implemented method of claim 15 , where the allocated reconfigurable processors are on a different processing node.

20. The computer-implemented method of claim 12 , wherein the pool of reconfigurable processors is dynamically scalable to meet the performance requirements of applications requesting e

Assignees

• Sambanova Systems Inc

Inventors

• Shenbagam Raghunath
• Kumar Ravinder

Classifications

• G06N3/098

  Distributed learning, e.g. federated learning · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0455

  Auto-encoder networks; Encoder-decoder networks · CPC title

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title