Multi-bit pulsed latch cell for use in an integrated circuit

Patent metadata

Field	Value
Publication number	US-9633156-B1
Application number	US-201615047033-A
Country	US
Kind code	B1
Filing date	Feb 18, 2016
Priority date	Jul 25, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

First claim

What is claimed is:

1. A multi-bit pulsed latch circuit for an integrated circuit design system, comprising:
a pulse generator for generating pulses; and
a plurality of latches that operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements.

2. The multi-bit pulsed latch circuit of claim 1 , wherein the pulse generator is shared among the plurality of latches.

3. The multi-bit pulsed latch circuit of claim 1 , wherein clock gating operations for the integrated circuit design system are performed within the multi-bit pulsed latch circuit.

4. The multi-bit pulsed latch circuit of claim 1 , wherein the plurality of latches are able to be stitched together so that the latches are scan testable.

5. The multi-bit pulsed latch circuit of claim 1 , further comprising an element for being able to couple to at least another multi-bit pulsed latch circuit in series so that the multi-bit pulsed latch circuit and the at least another multi-bit pulsed latch circuit are scan testable.

6. The multi-bit pulsed latch circuit of claim 1 , wherein the pulse generator and the plurality of latches are capable of being defined to characterize a multi-bit pulsed cell.

7. The multi-bit pulsed latch circuit of claim 6 , wherein the multi-bit pulsed cell is capable of being embodied in a cell technology file receivable by a logic synthesizer module of an integrated circuit design system for synthesizing an integrated circuit design.

8. The multi-bit pulsed latch circuit of claim 6 , wherein design constraints for defining the multi-bit pulsed latch cell at least include set up, hold, and clock-to-output timing operations.

9. A method of implementing a multi-bit pulsed latch circuit for an integrated circuit design system, comprising:
within the multi-bit pulsed latch circuit:
generating pulses by a pulse generator; and
coupling a plurality of latches that operate as storage elements to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements.

10. The method of claim 9 , wherein generating pulses by a pulse generator further comprises sharing the pulse generator among the plurality of latches.

11. The method of claim 9 , further comprising performing clock gating operations for the integrated circuit design system within the multi-bit pulsed latch circuit.

12. The method of claim 9 , wherein coupling a plurality of latches further comprises stitching together the plurality of latches so that the latches are scan testable.

13. The method of claim 9 , further comprising coupling at least another multi-bit pulsed latch circuit to the multi-bit pulsed latch circuit in series so that the multi-bit pulsed latch circuit and the at least another multi-bit pulsed latch circuit are scan testable.

14. The method of claim 9 , further comprising defining the pulse generator and the plurality of latches to characterize the multi-bit pulsed latch circuit as a multi-bit pulsed latch cell for a cell technology file receivable by a logic synthesizer module of an integrated circuit design system for synthesizing an integrated circuit design.

15. The method of claim 9 , further comprising defining the multi-bit pulsed latch circuit by using design constraints that at least include set up, hold, and clock-to-output timing operations.

16. A computer program product for implementing a multi-bit pulsed latch circuit for an integrated circuit design system, the computer program product comprising a computer usable medium having computer readable code physically embodied therein, said computer program product further comprising computer readable program code for, within the multi-bit pulsed latch circuit:
generating pulses by a pulse generator; and
coupling a plurality of latches that operate as storage elements to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements.

17. The computer program product of claim 16 , wherein the computer readable program code for generating pulses by a pulse generator further comprises computer readable program code for sharing the pulse generator among the plurality of latches.

18. The computer program product of claim 16 , further comprising computer readable program code for defining the pulse generator and the plurality of latches to characterize the multi-bit pulsed latch circuit for a cell technology file receivable by a logic synthesizer module of an integrated circuit design system for synthesizing an integrated circuit design.

19. The computer program product of claim 16 , further comprising computer readable program code for performing clock gating operations for the integrated circuit design system within the multi-bit pulsed latch circuit.

20. The computer program product of claim 16 , further comprising computer readable program code for stitching together the plurality of latches so that the latches are scan testable.

21. The computer program product of claim 16 , further comprising computer readable program code for coupling at least another multi-bit pulsed latch circuit to the multi-bit pulsed latch circuit in series so that the multi-bit pulsed latch circuit and the at least another multi-bit pulsed latch circuit are scan testable.

22. The computer program product of claim 16 , further comprising computer readable program code for defining the pulse generator and the plurality of latches to characterize the multi-bit pulsed latch circuit as a multi-bit pulsed latch cell for a cell technology file receivable by a logic synthesizer module of an integrated circuit design system for synthesizing an integrated circuit design.

23. The computer program product of claim 16 , further comprising computer readable program code for:
defining the multi-bit pulsed latch circuit by using design constraints that at least include set up, hold, and clock-to-output timing operations.

24. An integrated circuit design system for synthesizing an integrated circuit design, comprising:
a processor; and
a memory device coupled to the processor, wherein the memory device stores a plurality of instructions that when executed by the processor provides at least one software module that includes:
a logic synthesizer module that receives a circuit description and a cell technology file to generate functional logic of the integrated circuit design; and
wherein the cell technology file includes a characterization of a multi-bit pulsed latch circuit that functions as at least two flip flops and that includes a pulse generator for generating pulses and a plurality of latches coupled to the pulse generator.

25. The integrated circuit design system of claim 24 , wherein within the multi-bit pulsed latch circuit, the pulse generator is shared among the plurality of latches.

26. The integrated circuit design system of claim 24 , wherein clock gating operations for the integrated circuit design are performed within the multi-bit pulsed latch circuit.

27. The integrated circuit design system of claim 24 , wherein the plurality of latches are stitched together so that the latches are scan testable.

28. The integrated circuit design system of claim 24 , wherein the cell technology file that includes the characterization of the

Assignees

• Cirrus Logic Inc

Inventors

• Kumar Bhoodev
• Singh Saurabh
• Zhu Lei

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G01R31/318541

  Scan latches or cell details · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• G06F17/505 Primary

  Physics · mapped topic