Synchronous differential signaling protocol

Patent metadata

Field	Value
Publication number	US-2016344536-A1
Application number	US-201615159760-A
Country	US
Kind code	A1
Filing date	May 19, 2016
Priority date	May 21, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.

First claim

What is claimed is:

1 . A method of communicating between a first device and a second device, comprising:
communicating, by the first device with the second device, synchronously over a differential line to transmit data in a frame, wherein the first device and the second device communicate synchronously using the same clock signal.

2 . The method of claim 1 , further comprising recovering, by the first device, a clock signal of the second device, wherein the first device comprises a slave device and the second device comprises a master device.

3 . The method of claim 2 , wherein the step of recovering the clock signal comprises receiving, by the first device from the second device, synchronizing bits for detecting the clock signal of the second device.

4 . The method of claim 3 , wherein the step of recovering the clock signal further comprises transmitting, by the first device, a predetermined pattern to the second device; and receiving, by the first device, a predetermined acknowledgment pattern to complete initialization of the connection.

5 . The method of claim 1 , wherein the step of communicating comprises adjusting allocation of downlink slots and uplink slots within the frame.

6 . The method of claim 5 , wherein the step of adjusting allocation comprises adjusting a number of turnarounds within the frame.

7 . The method of claim 5 , wherein the step of adjusting allocation comprises adjusting a location of turnarounds within the frame.

8 . The method of claim 1 , wherein the step of communicating comprises adjusting a position of control bits within the frame.

9 . The method of claim 1 , wherein the step of communicating comprises adjusting a frequency of the clock signal.

10 . The method of claim 1 , wherein the step of communicating comprises receiving, within the frame, a command, wherein the command determines an organization of data within the frame.

11 . The method of claim 10 , wherein the step of communicating comprises receiving a command indicating a burst configuration for the frame, wherein the burst configuration configures the frame for writing control data when digital data is not present.

12 . The method of claim 1 , wherein the step of communicating comprises receiving, within control word bits of the frame, an interrupt bit indicating a received interrupt.

13 . The method of claim 1 , further comprising detecting, by the first device, a reset command from the second device by detecting a predefined potential on the differential line.

14 . An apparatus, comprising:
a first device configured to communicate synchronously with a second device over a differential communications path by transmitting data in a frame, wherein the first device and the second device communicate using a same clock signal.

15 . The apparatus of claim 14 , wherein the first device is configured to recover a clock signal of the second device, wherein the first device comprises a slave device and the second device comprises a master device.

16 . The apparatus of claim 15 , wherein the first device is configured to receiving synchronizing bits for detecting the clock signal of the second device.

17 . The apparatus of claim 16 , wherein the first device is configured to transmit a predetermined pattern to the second device, and to receive a predetermined acknowledgment pattern to initialize the communications path.

18 . The apparatus of claim 14 , wherein the first device is configured to communicate by adjusting allocation of downlink slots and uplink slots within the frame.

19 . The apparatus of claim 18 , wherein the first device is configured to adjust allocation by adjusting a number of turnarounds within the frame.

20 . The apparatus of claim 18 , wherein the first device is configured to adjust allocation by adjusting a location of turnarounds within the frame.

21 . The apparatus of claim 14 , wherein the first device is configured to communicate by adjusting a position of control bits within the frame.

22 . The apparatus of claim 14 , wherein the first device is configured to communicate by adjusting a frequency of the clock signal for the synchronous, differential communications path.

23 . The apparatus of claim 14 , wherein the first device is configured to communicate by receiving, within the frame, a command, wherein the command determines an organization of data within the frame.

24 . The apparatus of claim 23 , wherein the first device is configured to communicate by receiving a command indicating a burst configuration for the frame, wherein the burst configuration configures the frame for writing control data when digital data is not present.

25 . The apparatus of claim 14 , wherein the first device is configured to communicate by receiving, within control word bits of the frame, an interrupt bit indicating a received interrupt.

26 . The apparatus of claim 14 , wherein the first device is configured to communicate by detecting a reset command from the second device by detecting a predefined potential on the differential line.

27 . A system, comprising:
a master device; a slave device; and a communications path between the master device and the slave device, wherein the master device and the slave device are configured to communicate using frames transmitted in synchronous, differential signals over the communications path using a same clock signal.

28 . The system of claim 27 , wherein the slave device is configured to recover a clock signal of the master device.

29 . The system of claim 28 , wherein the master device is configured to transmit synchronizing bits for initializing communications over the communications path, and wherein the slave device is configured to recover the clock signal based, at least in part, on the synchronizing bits.

30 . The system of claim 29 , wherein the slave device is configured to transmit a predetermined pattern to the master device, wherein the master device is configured to receive the predetermined pattern and to transmit, in response, a predetermined acknowledgement pattern to initialize communications over the communications path.

31 . The system of claim 27 , wherein the master device and the slave device are configured to communicate by adjusting allocation of downlink slots and uplink slots within the frame.

32 . The system of claim 31 , wherein the master device and the slave device are configured to adjust allocation by adjusting a number of turnarounds within the frame.

33 . The system of claim 31 , wherein the master device and the slave device are configured to adjust allocation by adjusting a location of turnarounds within the frame.

34 . The system of claim 27 , wherein the master device and the slave device are configured to communicate by adjusting a position of control bits within the frame.

35 . The system of claim 27 , wherein the master device and the slave device are configured to communicate by adjusting a frequency of the communications path.

36 . The system of claim 27 , wherein the master device and the slave device are configured to communicate by transmitting a command that determines an organization of data within the frame.

37 . The syste

Assignees

• Cirrus Logic Int Semiconductor Ltd

Inventors

• Kumar Bhoodev
• Ramakrishnan Muraleedharan
• Oppula Vivek
• Hoff Thomas
• Zwart Willem

Classifications

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title