Highly linear input and output rail-to-rail amplifier

Patent metadata

Field	Value
Publication number	US-11082012-B2
Application number	US-201916409580-A
Country	US
Kind code	B2
Filing date	May 10, 2019
Priority date	May 10, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

First claim

The invention claimed is:

1. A method for maintaining a constant bias current across a voltage swing of an input signal received by input transconductors of an amplifier, comprising:
generating a supply side current mirror gate voltage as a function of input signal voltage; and
using the gate voltage for controlling bias current sources to the input transconductors, wherein a bias current of the input transconductors is maintained as constant at a summing node of the amplifier across the voltage swing of the input signal.

2. The method of claim 1 , further comprising:
wherein when the input signal voltage is low, the gate voltage turns off the bias current sources to the input transconductors and tail current sources of the input transconductors; and
wherein when the input signal voltage is not low, the gate voltage turns on the bias current sources to the input transconductors and the tail current sources of the input transconductors.

3. The method of claim 1 , further comprising:
wherein an integrated circuit comprises the amplifier, wherein the integrated circuit includes an input pin for connection to a sensor external to the integrated circuit, wherein the integrated circuit includes a switch connected between the pin and gate terminals of input devices of the amplifier, wherein the input devices comprise the input transconductors;
comparing a voltage on the pin with a reference generated internally to the integrated circuit; and
controlling the switch, based on said comparing, to disconnect the input transconductors from the pin in response to detecting a short condition at the pin.

4. The method of claim 1 , further comprising:
wherein a transimpedance amplifier (TIA) comprises the amplifier and a transimpedance gain element, wherein the TIA receives a current from a sensor and outputs a voltage proportional to the sensor current based on a value of the transimpedance gain element;
applying an external direct current (DC) current from an external DC current source to a non-inverting input of the TIA;
measuring a voltage across the transimpedance gain element using at least two analog-to-digital converters (ADCs) within the TIA;
determining the value of the transimpedance gain element by using the measured voltage and the external DC current; and
using a digital calibration loop within the TIA to determine a calibrated value for the transimpedance gain element using an output of the digital calibration loop.

5. The method of claim 1 , further comprising:
averaging source voltages of at least two of the transconductors to provide an average source voltage;
applying the average source voltage to wells of input devices of the at least two transconductors to reduce back bias effect; and
wherein the input devices are laid out in a same well and have a common centroid to cancel out process mismatches.

6. The method of claim 1 , further comprising:
wherein a first one or more of the input transconductors process the input signal when the input signal voltage is high and a second one or more of the input transconductors process the input signal when the input signal voltage is low;
using a first current digital-to-analog converter (I-DAC) to trim an offset of the first one or more transconductors;
using a second I-DAC to trim an offset of the second one or more transconductors; and
wherein said using the first and second I-DACs attains low offsets across a rail-to-rail input common mode range of the amplifier.

7. An apparatus, comprising:
an amplifier comprising:
input transconductors that receive an input signal, the input signal having a voltage swing;
a supply side current mirror that generates a gate voltage as a function of input signal voltage; and
current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current at a summing node of the amplifier across the voltage swing of the input signal.

8. The apparatus of claim 7 , further comprising:
wherein when the input signal voltage is low, the gate voltage turns off the bias current sources to the input transconductors and tail current sources of the input transconductors; and
wherein when the input signal voltage is not low, the gate voltage turns on the bias current sources to the input transconductors and the tail current sources of the input transconductors.

9. The apparatus of claim 7 , further comprising:
an input pin for connection to a sensor external to an integrated circuit that comprises the amplifier;
a comparator that compares a voltage on the pin with a reference generated internally to the integrated circuit;
a switch connected between the pin and gate terminals of input devices of the amplifier, wherein the input devices comprise the input transconductors; and
wherein the comparator output voltage controls the switch to disconnect the input transconductors from the pin in response to detecting a short condition at the pin.

10. The apparatus of claim 7 , further comprising:
a transimpedance amplifier (TIA) comprising:
the amplifier;
a transimpedance gain element; and
at least two analog-to-digital converters (ADCs);

wherein the TIA receives a current from a sensor and outputs a voltage proportional to the sensor current based on a value of the transimpedance gain element;
wherein the at least two ADCs are usable for measuring a voltage across the transimpedance gain element in response to application of an external direct current (DC) current from an external DC current source to a non-inverting input of the TIA;
wherein a value of the transimpedance gain element is determinable by using the measured voltage and the external DC current; and
wherein a calibrated value for the transimpedance gain element is determinable using an output of a digital calibration loop within the TIA.

11. The apparatus of claim 7 , further comprising:
resistors that average source voltages of at least two of the transconductors to provide an average source voltage and that apply the average source voltage to wells of input devices of the at least two transconductors to reduce back bias effect; and
wherein the input devices are laid out in a same well and have a common centroid to cancel out process mismatches.

12. The apparatus of claim 7 , further comprising:
wherein the input transconductors comprise:
a first one or more transconductors that process an input voltage when the input voltage is high; and
a second one or more transconductors that process the input voltage when the input voltage is low;

a first current digital-to-analog converter (I-DAC) used to trim an offset of the first one or more transconductors;
a second I-DAC used to trim an offset of the second one or more transconductors; and
wherein use of the first and second I-DACs attains low offsets across a rail-to-rail input common mode range over which the amplifier operates.

13. A method for increasing linearity of an amplifier having transconductance-cancelling transconductors, comprising:
averaging source voltages of the transconductance-cancelling transconductors to provide an average source voltage;
applying the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect; and
wherein the input devices are laid out in a same well and have a common centroid to cancel out process mismatches.

14. The method of claim 13 , further comprising:
generating a supply side current mirror gate voltage as a function of input signal voltage; and
using the gate voltage for providing a bias current of the transconductor

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Pandey Vaibhav
• Kumar Bhoodev

Classifications

• H03F2203/45538

  the IC comprising balancing means, e.g. trimming means · CPC title

• H03F2203/45354

  the AAC comprising offset means · CPC title

• H03F2203/45152

  Balancing means being added at the input of a dif amp to reduce the offset of the dif amp · CPC title

• H03F2203/45038

  One or more current sources are added or changed as balancing means to reduce the offset of the dif amp · CPC title

• H03F2203/45318

  the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled · CPC title