Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
US-12406931-B2 · Sep 2, 2025 · US
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Kothari Hiten patents
Kothari Hiten is listed as an inventor on 19 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kothari Hiten |
| Total patents | 19 |
| First publication | Sep 22, 2015 |
| Latest publication | Sep 2, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
US-12261122-B2 · Mar 25, 2025 · US
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
US-2024347465-A1 · Oct 17, 2024 · US
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
US-2024006322-A1 · Jan 4, 2024 · US
Resistive random access memory device and methods of fabrication
US-11489112-B2 · Nov 1, 2022 · US
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
US-2022310516-A1 · Sep 29, 2022 · US
Resistive random access memory device with switching multi-layer stack and methods of fabrication
US-11430948-B2 · Aug 30, 2022 · US
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
US-11393754-B2 · Jul 19, 2022 · US
A resistive random access memory device with switching multi-layer stack and methods of fabrication
US-2020203603-A1 · Jun 25, 2020 · US
A resistive random access memory device and methods of fabrication
US-2020203602-A1 · Jun 25, 2020 · US
Recent patents
Latest publications not already listed above.
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
US-2020105672-A1 · Apr 2, 2020 · US
Chip assemblies employing solder bonds to back-side lands including an electrolytic nickel layer
US-2019237391-A1 · Aug 1, 2019 · US
Anchored interconnect
US-9818710-B2 · Nov 14, 2017 · US
Preservation of fine pitch redistribution lines
US-9721886-B2 · Aug 1, 2017 · US
Anchored interconnect
US-2017069589-A1 · Mar 9, 2017 · US
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
US-9530740-B2 · Dec 27, 2016 · US
3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
US-9449913-B2 · Sep 20, 2016 · US
3d interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
US-2015364425-A1 · Dec 17, 2015 · US
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
US-9142510-B2 · Sep 22, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 19 |
| Lee Kevin J | 2 |
| Bohr Mark T | 2 |
| Yeoh Andrew W | 2 |
| Pelto Christopher M | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/724 | 12 |
| H10W20/20 | 12 |
| H10W20/40 | 11 |
| H10W20/081 | 8 |
| H10W20/056 | 8 |