Anchored interconnect

Patent metadata

Field	Value
Publication number	US-9818710-B2
Application number	US-201415120788-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Mar 28, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An embodiment includes a semiconductor structure comprising: a backend portion including a plurality of metal layers between bottom and top metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another; an insulator layer directly contacting the top surface; and a via coupling a contact bump to the top metal layer portion; wherein a first vertical axis, orthogonal to a substrate coupled to the backend portion, intercepts the contact bump, the nitride layer, the via, and the top metal layer portion. Other embodiments are described herein.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a frontend portion including a device layer on a substrate;
a backend portion including a bottom metal layer, a top metal layer, and a plurality of metal layers between the bottom and top metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another;
a nitride layer directly contacting the top surface directly adjacent the first sidewall surface at a first location and directly contacting the top surface directly adjacent the second sidewall surface at a second location; and
a contact bump and a via coupling the contact bump to the top metal layer portion;
wherein (a) the backend portion includes no metal layer between the bottom metal layer and a top of the frontend portion; (b) the backend portion includes no metal layer between the top metal layer and the top of the backend portion; (c) the via directly contacts the top metal layer portion directly beneath the nitride layer at both of the first and second locations; (d) a first vertical axis, orthogonal to the substrate, intercepts the contact bump, the nitride layer, the via, and the top metal layer portion; and (e) a second vertical axis, orthogonal to the substrate, intercepts the contact bump, the nitride layer, a dielectric, and the top surface.

2. The structure of claim 1 , wherein the via directly interfaces the top surface along a curved line that extends from the first location to the second location.

3. The structure of claim 2 , wherein the top metal layer portion includes an interconnect line.

4. The structure of claim 2 , wherein the curved line is generally parabolic having a parabolic vertex located directly below the via and the contact bump and located between the first and second locations and the substrate.

5. The structure of claim 1 , wherein a horizontal axis, orthogonal to the first vertical axis, intercepts the nitride layer, the first and second sidewall surfaces, and the via.

6. A semiconductor structure comprising:
a backend portion including a plurality of metal layers between bottom and top metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another;
an insulator layer directly contacting the top surface; and
a via coupling a contact bump to the top metal layer portion;
wherein (a) a first vertical axis, orthogonal to a substrate coupled to the backend portion, intercepts the contact bump, the insulator layer, the via, and the top metal layer portion, (b) the first vertical axis intersects the via above the insulator layer and below the insulator layer.

7. The structure of claim 6 , wherein the via directly contacts the top metal layer portion directly beneath the insulator layer at first and second locations.

8. The structure of claim 7 , wherein the via directly interfaces the top surface along a curving line that extends from the first location to the second location.

9. The structure of claim 8 , wherein the curving line is generally parabolic having a parabolic vertex located directly below the via and the contact bump and located between the first and second locations and the substrate.

10. The structure of claim 6 , wherein the top metal layer portion includes an interconnect line.

11. The structure of claim 6 , wherein:
a second vertical axis, orthogonal to the substrate, intercepts the contact bump, the insulator layer, a dielectric, and the top surface; and
the insulator layer is between the dielectric and the top surface.

12. The structure of claim 11 , wherein:
a horizontal axis, orthogonal to the first vertical axis, intercepts the insulator layer, the first and second sidewall surfaces, the dielectric, and the via; and
the dielectric includes a member selected from the group consisting of an oxide, a nitride, or a photodefinable polymer.

13. The structure of claim 6 , wherein a horizontal axis, orthogonal to the first vertical axis, intercepts the insulator layer, the first and second sidewall surfaces, and the via.

14. The structure of claim 6 , wherein the insulator layer includes a nitride.

15. A method comprising:
forming a frontend portion, including a device layer, on a substrate;
forming a plurality of metal layers on the frontend portion;
forming a top metal layer on the plurality of metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another;
forming a nitride layer on the top surface;
forming a via on top of the top metal layer portion;
forming a contact bump on the via;
wherein (a) a first vertical axis, orthogonal to the substrate, intercepts the contact bump, the nitride layer, the via, and the top metal layer portion, and (b) the via includes a member selected from the group consisting of copper, aluminum, or tungsten.

16. The method of claim 15 , wherein the via directly contacts the top metal layer portion directly beneath the nitride layer at first and second locations.

17. The method of claim 16 , wherein the via directly interfaces the top surface along a curving line that extends from the first location to the second location.

18. The method of claim 17 , wherein the curving line is generally parabolic having a parabolic vertex located directly below the via and the contact bump and located between the first and second locations and the substrate.

19. The method of claim 15 , wherein the top metal layer portion includes an interconnect line.

20. The method of claim 15 , wherein a second vertical axis, orthogonal to the substrate, intercepts the contact bump, the nitride layer, a dielectric, and the top surface.

21. The method of claim 15 , wherein a horizontal axis, orthogonal to the first vertical axis, intercepts the nitride layer, the first and second sidewall surfaces, and the via.

22. The structure of claim 1 , wherein a portion of the dielectric that intercepts the second vertical axis is between the nitride layer and the via.

23. The structure of claim 12 , wherein the photodefinable polymer includes a member selected from the group consisting of a novolak resin or poly(hydroxystyrene).

Assignees

• Intel Corp

Inventors

• Kang Jiho
• Kothari Hiten
• Montarou Carole C
• Yeoh Andrew W

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title