3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach

Patent metadata

Field	Value
Publication number	US-9530740-B2
Application number	US-201514836828-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Oct 28, 2011
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

First claim

What is claimed is:

1. A 3D interconnect structure comprising:
a semiconductor substrate having a front surface and a back surface;
a first passivation layer on the back surface;
an insulating layer on the first passivation layer;
a dual damascene structure comprising a via and a redistribution layer (RDL), the via extending through the first passivation layer and extending through the semiconductor substrate between the front and back surfaces and, the RDL disposed in a trench opening in the insulating layer and on the first passivation layer, the RDL electrically coupled to the via, wherein a portion of the RDL is over the via and a portion of the RDL is not over the via; and
a second passivation layer formed over the RDL and the insulating layer, wherein the second passivation layer has an opening exposing a portion of the portion of the RDL not over the via, but not exposing the portion of the RDL over the via.

2. The 3D interconnect structure of claim 1 , wherein the second passivation layer comprises silicon nitride.

3. The 3D interconnect structure of claim 1 , wherein the dual damascene structure further comprises an insulating liner layer formed on side surfaces of the via and trench opening, and not formed on bottom surfaces of the via and trench opening.

4. The 3D interconnect structure of claim 3 , wherein the dual damascene structure further comprises a continuous barrier layer formed on the bottom surfaces of the via and trench opening, and on the insulating liner layer formed on the side surfaces of the via and trench opening.

5. The 3D interconnect structure of claim 1 , further comprising:
an landing pad formed in the opening of the second passivation layer; and
a conductive bump formed on the landing pad.

6. The 3D interconnect structure of claim 1 , wherein the insulating layer is an oxide layer.

7. The 3D interconnect structure of claim 6 , wherein the first passivation layer is a hermetic layer.

8. The 3D interconnect structure of claim 7 , wherein hermetic layer is a layer selected from the group consisting of a silicon nitride layer and a silicon carbide layer.

9. A 3D package comprising:
a base substrate;
a chip stack formed over the base substrate; wherein the chip stack includes a chip comprising:
a semiconductor substrate having a front surface and a back surface;
a first passivation layer on the back surface;
an insulating layer on the first passivation layer;
a plurality of dual damascene structures, each of the dual damascene structures comprising a via and a redistribution layer (RDL) electrically coupled to the via, each of the vias extending through the passivation layer and extending through the semiconductor substrate between the front and back surfaces, and each of the RDLs disposed in a corresponding trench opening in the insulating layer and on the first passivation layer, wherein a portion of the RDLs is over the vias and a portion of the RDLs is not over the vias; and

a second passivation layer formed over the RDLs, wherein the second passivation layer has openings exposing a portion of the portion of the RDLs not over the vias, but not exposing the portion of the RDLs over the vias.

10. The 3D package of claim 9 , wherein the chip is a logic chip.

11. The 3D package of claim 9 , further comprising a system comprising a bus communicatively coupled to the 3D package.

12. The 3D package of claim 9 , wherein the second passivation layer comprises silicon nitride.

13. The 3D package of claim 9 , wherein the dual damascene structures further comprise an insulating liner layer formed on side surfaces of the vias and the trench openings, and not formed on bottom surfaces of the vias and the trench openings.

14. The 3D package of claim 13 , wherein the dual damascene structures further comprise a continuous barrier layer formed on the bottom surfaces of the vias and the trench openings, and on the insulating liner layer formed on the side surfaces of the vias and the trench openings.

15. The 3D package of claim 9 , wherein the insulating layer is an oxide layer.

16. The 3D interconnect structure of claim 15 , wherein the first passivation layer is a hermetic layer.

17. The 3D interconnect structure of claim 16 , wherein hermetic layer is a layer selected from the group consisting of a silicon nitride layer and a silicon carbide layer.

18. The 3D package of claim 9 , further comprising:
a plurality of landing pads formed in the openings of the second passivation layer.

19. The 3D package of claim 18 , further comprising:
a plurality of conductive bumps formed on the plurality of landing pads.

20. The 3D package of claim 18 , wherein the plurality of landing pads is coupled with a corresponding plurality of landing pads of a memory chip.

Assignees

• Intel Corp

Inventors

• Lee Kevin J
• Bohr Mark T
• Yeoh Andrew W
• Pelto Christopher M
• Kothari Hiten
• Sattiraju Seshu V
• Ma Hang-Shing

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title