Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-2020105672-A1
Application number	US-201816147541-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon; a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon; a first dielectric etch stop layer directly on and continuous over the trench insulating layers and the gate insulating layers; a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer; an interlayer dielectric material on the second dielectric etch stop layer; an opening in the interlayer dielectric material, in the second dielectric etch stop layer, in the first dielectric etch stop layer, and in one of the trench insulating layers; and a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures.

2 . The integrated circuit structure of claim 1 , wherein the second dielectric etch stop layer comprises aluminum and oxygen.

3 . The integrated circuit structure of claim 1 , wherein the first etch stop layer comprises nitrogen, silicon and hydrogen.

4 . The integrated circuit structure of claim 1 , wherein the interlayer dielectric material comprises silicon, oxygen, carbon and hydrogen.

5 . The integrated circuit structure of claim 1 , wherein the trench insulating layers comprise silicon carbide, and the gate insulating layers comprise silicon nitride.

6 . The integrated circuit structure of claim 1 , further comprising:
a plurality of dielectric spacers alternating with the plurality of gate structures and the plurality of conductive trench contact structures, wherein the first dielectric etch stop layer is directly on the plurality of dielectric spacers.

7 . The integrated circuit structure of claim 1 , wherein the plurality of conductive trench contact structures and the plurality of gate structures are on a semiconductor fin.

8 . The integrated circuit structure of claim 1 , wherein the conductive structure includes an upper conductive line and a lower conductive via.

9 . An integrated circuit structure, comprising:
a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon; a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon; a first dielectric etch stop layer directly on and continuous over the trench insulating layers and the gate insulating layers; a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer; an interlayer dielectric material on the second dielectric etch stop layer; an opening in the interlayer dielectric material, in the second dielectric etch stop layer, in the first dielectric etch stop layer, and in one of the gate insulating layers; and a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the gate structures.

10 . The integrated circuit structure of claim 9 , wherein the second dielectric etch stop layer comprises aluminum and oxygen.

11 . The integrated circuit structure of claim 9 , wherein the first etch stop layer comprises nitrogen, silicon and hydrogen.

12 . The integrated circuit structure of claim 9 , wherein the interlayer dielectric material comprises silicon, oxygen, carbon and hydrogen.

13 . The integrated circuit structure of claim 9 , wherein the trench insulating layers comprise silicon carbide, and the gate insulating layers comprise silicon nitride.

14 . The integrated circuit structure of claim 9 , further comprising:
a plurality of dielectric spacers alternating with the plurality of gate structures and the plurality of conductive trench contact structures, wherein the first dielectric etch stop layer is directly on the plurality of dielectric spacers.

15 . The integrated circuit structure of claim 9 , wherein the plurality of conductive trench contact structures and the plurality of gate structures are on a semiconductor fin.

16 . The integrated circuit structure of claim 9 , wherein the conductive structure includes an upper conductive line and a lower conductive via.

17 . A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon; forming a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon; forming a first dielectric etch stop layer directly on and continuous over the trench insulating layers and the gate insulating layers; forming a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer; forming an interlayer dielectric material on the second dielectric etch stop layer; forming an opening in the interlayer dielectric material using a first dry or plasma etch process; extending the opening in the second dielectric etch stop layer using a wet etch process; further extending the opening in the first dielectric etch stop layer and in one of the trench insulating layers using a second dry or plasma etch process; and forming a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures.

18 . The method of claim 17 , wherein the second dielectric etch stop layer comprises aluminum and oxygen.

19 . The method of claim 17 , wherein the first etch stop layer comprises nitrogen, silicon and hydrogen.

20 . The method of claim 17 , wherein the interlayer dielectric material comprises silicon, oxygen, carbon and hydrogen, and wherein the trench insulating layers comprise silicon carbide.

21 . A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon; forming a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon; forming a first dielectric etch stop layer directly on and continuous over the trench insulating layers and the gate insulating layers; forming a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer; forming an interlayer dielectric material on the second dielectric etch stop layer; forming an opening in the interlayer dielectric material using a first dry or plasma etch process; extending the opening in the second dielectric etch stop layer using a wet etch process; further extending the opening in the first dielectric etch stop layer and in one of the gate insulating laye

Assignees

• Intel Corp

Inventors

• Madhavan Atul
• Kybert Nicholas J
• Haran Mohit K
• Kothari Hiten

Classifications

• H01L21/02178

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L21/76802

  Electricity · mapped topic

• H01L21/823437

  Electricity · mapped topic