Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness

Patent metadata

Field	Value
Publication number	US-12099378-B2
Application number	US-202217963129-A
Country	US
Kind code	B2
Filing date	Oct 10, 2022
Priority date	Feb 28, 2020
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

First claim

What is claimed is:

1. A computer system comprising a graphics processing unit (GPU), the GPU comprising:
a processor configured to:
execute graphics rendering commands for a bin visibility pass and a non-bin-visibility pass; and
operate at an operating point corresponding to an operating voltage and an operating frequency; and

a power management circuit configured to:
in response to the executed graphics rendering commands:
control the operating point of the processor;
set a bin-visibilty operating point for the bin visibility pass that is different from an operating point for the non-bin-visibility pass;
identify the graphics rendering command as a command for the bin visibility pass;
adjust the operating point of the processor to the bin-visibility operating point in response to the identification;
subsequently identify a graphics rendering command as a command for a non-bin-visibilty pass; and
adjust the operating point of the processor to the non-bin-visibility pass in response to the subsequent identification.

2. The computer system of claim 1 , wherein the non-bin-visibility pass comprises at least one of a rendering pass and a resolve pass.

3. The computer system of claim 1 , wherein the bin-visibility point is higher than the non-bin-visibility operating point.

4. The computer system of claim 1 , wherein the power management circuit is configured to adjust the operating point of the processor in stages, first adjusting the operating frequency and then adjusting the operating voltage.

5. The computer system of claim 1 , wherein the computer system is one of: a head-mounted display, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

6. The computer system of claim 3 , wherein the operating frequency corresponding to the bin-visibility operating point is higher than the operating frequency corresponding to the non-bin-visibility operating point.

7. The computer system of claim 3 , wherein the operating voltage corresponding to the bin-visibility operating point is higher than the operating voltage corresponding to the non-bin-visibility operating point.

8. The computer system of claim 3 , wherein:
the operating frequency corresponding to the bin-visibility operating point is higher than the operating frequency corresponding to the non-bin-visibility operating point; and
the operating voltage corresponding to the bin-visibility operating point is higher than the operating voltage corresponding to the non-bin-visibility operating point.

9. A computer-implemented method for a system comprising a graphics processing unit (GPU), the method comprising:
executing, by a processor, graphics rendering commands for a bin visibility pass and a non-bin-visibility pass;
operating, by the processor, at an operating point corresponding to an operating voltage and an operating frequency;
in response to the executed graphics rendering commands:
controlling, by a power management circuit, the operating point of the processor; setting, by the power management circuit, a bin-visibilty operating point for the bin visibility pass that is different from an operating point for the non-bin-visibility pass;
identifying, by the power managemement circuit, the graphics rendering command as a command for the bin visibility pass;
adjusting, by the power managemement circuit, the operating point of the processor to the bin-visibility operating point in response to the identification;
subsequently, by the power managemement circuit, identifying a graphics rendering command as a command for a non-bin-visibilty pass; and
adjusting, by the power managemement circuit, the operating point of the processor to the non-bin-visibility pass in response to the subsequent identification.

10. The method of claim 9 , wherein the non-bin-visibility pass comprises at least one of a rendering pass and a resolve pass.

11. The method of claim 9 , wherein the bin-visibility point is higher than the non-bin-visibility operating point.

12. The method of claim 9 , comprising adjusting the operating point of the processor in stages, first adjusting the operating frequency and then adjusting the operating voltage.

13. The method of claim 11 , wherein the operating frequency corresponding to the bin-visibility operating point is higher than the operating frequency corresponding to the non-bin-visibility operating point.

14. The method of claim 11 , wherein the operating voltage corresponding to the bin-visibility operating point is higher than the operating voltage corresponding to the non-bin-visibility operating point.

15. The method of claim 11 , wherein:
the operating frequency corresponding to the bin-visibility operating point is higher than the operating frequency corresponding to the non-bin-visibility operating point; and
the operating voltage corresponding to the bin-visibility operating point is higher than the operating voltage corresponding to the non-bin-visibility operating point.

Assignees

• Qualcomm Inc

Inventors

• Jose Edwin
• Jenkal Ravi
• Kim Donghyun

Classifications

• G06F9/4837

  time dependent · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title