Low latency synchronization scheme for mesochronous DDR system

Patent metadata

Field	Value
Publication number	US-9437278-B2
Application number	US-201514816820-A
Country	US
Kind code	B2
Filing date	Aug 3, 2015
Priority date	May 24, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

First claim

What is claimed is:

1. A memory interface, comprising:
a memory controller configured to output a data clock signal and data synchronized with the data clock signal; and
a synchronization circuit configured to receive the data, the data clock signal, and a clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, to synchronize the sampled data with the clean clock signal, to output the synchronized sampled data, to track a phase drift between the data clock signal and the clean clock signal, and to pull in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

2. The memory interface of claim 1 , wherein the synchronization circuit is further configured to push out the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a second value in a second direction, the second direction being opposite from the first direction.

3. The memory interface of claim 1 , wherein the synchronization circuit is configured to track the phase drift between the data clock signal and the clean clock signal by detecting a phase difference between the data clock signal and the clean clock signal, and tracking changes in the detected phase difference.

4. The memory interface of claim 3 , wherein the detected phase difference has a granularity of approximately a quarter of a clock cycle of the clean clock signal.

5. The memory interface of claim 4 , wherein the synchronization circuit is configured to pull in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the detected phase difference changes by three or four quarters of a clock cycle in the first direction.

6. The memory interface of claim 4 , wherein the synchronization circuit is configured to push out the output of the synchronized sampled data by one clock cycle of the clean clock signal if the detected phase difference changes by three or four quarters of a clock cycle in the second direction.

7. The memory interface of claim 1 , wherein the synchronization circuit is located near a periphery of a chip, and the memory controller is located approximately at a center of the chip.

8. The memory interface of claim 1 , further comprising a cleanup phased-locked loop (PLL) configured to receive a reference clock signal, and to generate the clean clock signal based on the reference clock signal, the reference clock signal and the data clock signal being derived from a common clock signal.

9. A method for data synchronization, comprising:
receiving data, a data clock signal, and a clean clock signal;
sampling the data using the data clock signal;
synchronizing the sampled data with the clean clock signal;
outputting the synchronized sampled data;
tracking a phase drift between the data clock signal and the clean clock signal; and
pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

10. The method of claim 9 , further comprising pushing out the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a second value in a second direction, the second direction being opposite from the first direction.

11. The method of claim 9 , wherein tracking the phase drift between the data clock signal and the clean clock signal further comprises:
detecting a phase difference between the data clock signal and the clean clock signal; and
tracking changes in the detected phase difference.

12. The method of claim 11 , wherein the detected phase difference has a granularity of approximately a quarter of a clock cycle of the clean clock signal.

13. The method of claim 12 , wherein pulling in the output of the synchronized sampled data comprises pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the detected phase difference changes by three or four quarters of a clock cycle in the first direction.

14. The memory interface of claim 12 , further comprising pushing out the output of the synchronized sampled data by one clock cycle of the clean clock signal if the detected phase difference changes by three or four quarters of a clock cycle in the second direction.

15. An apparatus for data synchronization, comprising:
means for receiving data, a data clock signal, and a clean clock signal;
means for sampling the data using the data clock signal;
means for synchronizing the sampled data with the clean clock signal;
means for outputting the synchronized sampled data;
means for tracking a phase drift between the data clock signal and the clean clock signal; and
means for pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

16. The apparatus of claim 15 , further comprising means for pushing out the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a second value in a second direction, the second direction being opposite from the first direction.

17. The apparatus of claim 15 , wherein the means for tracking the phase drift between the data clock signal and the clean clock signal further comprises:
means for detecting a phase difference between the data clock signal and the clean clock signal; and
means for tracking changes in the detected phase difference.

18. The apparatus of claim 17 , wherein the detected phase difference has a granularity of approximately a quarter of a clock cycle of the clean clock signal.

19. The apparatus of claim 18 , wherein the means for pulling in the output of the synchronized sampled data comprises means for pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the detected phase difference changes by three or four quarters of a clock cycle in the first direction.

20. The apparatus of claim 18 , further comprising means for pushing out the output of the synchronized sampled data by one clock cycle of the clean clock signal if the detected phase difference changes by three or four quarters of a clock cycle in the second direction.

21. A memory interface, comprising:
a plurality of synchronization circuits; and
a memory controller configured to output a clock signal and a calibration signal to each of the plurality of synchronization circuits;
wherein each of the plurality of synchronization circuits is configured to detect a phase difference between the calibration signal and the clock signal at the synchronization circuit, and to report the detected phase difference to the memory controller; and
wherein the memory controller is configured to determine whether outputs of the synchronization circuits are offset by one clock cycle of the clock signal based on the detected phase differences from the plurality of synchronization circuits, and to instruct each of one or more of the synchronization circuits to pull in or push out the respective output by one clock cycle of the clock signal if a determination is made that the outputs of the synchronization circuits are offset by one clock cycle of the clock signal.

22. The memory interface of claim 21 , wherein each of the synchronization circuits

Assignees

• Qualcomm Inc

Inventors

• Jose Edwin
• Drop Michael
• Huang Xuhao
• Sankuratri Raghu
• Sriramagiri Deepti Vijayalakshmi
• Pedrali-Noy Marzio

Classifications

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C2207/2254

  Calibration · CPC title