Progressive Flush of Cache Memory

Patent metadata

Field	Value
Publication number	US-2019266098-A1
Application number	US-201815908637-A
Country	US
Kind code	A1
Filing date	Feb 28, 2018
Priority date	Feb 28, 2018
Publication date	Aug 29, 2019
Grant date	—

Abstract

Various embodiments include methods and devices for implementing progressive flush of a cache memory of a computing device. Various embodiments may include determining an activity state of a region of the cache memory, issuing a start cache memory flush command in response to determining that the activity state of the region is idle, flushing the region in response to the start cache memory flush command, determining that the activity state of the region is active, issuing an abort cache memory flush command in response to determining that the activity state of the region is active, and aborting flushing the region in response to the abort cache memory flush command.

First claim

1 . A method for conducting a progressive flush of a cache memory of a computing device, comprising:
determining an activity state of a region of the cache memory; issuing a start cache memory flush command in response to determining that the activity state of the region is idle; flushing the region in response to the start cache memory flush command; determining whether the activity state of the region is or is about to be active; issuing an abort cache memory flush command in response to determining that the activity state of the region is or is about to be active; and in response to the abort cache memory flush command:
continuing flushing a first section of the region that is undergoing flush; and
aborting flushing the region in response to completing flushing the first section.

2 . The method of claim 1 , further comprising receiving an indicator of an activity state of a client associated with the region,
wherein determining an activity state of a region of the cache memory comprises determining the activity state of the region based on the activity state of the client.

3 . The method of claim 1 , further comprising receiving an indicator of an expected activity state of a client associated with the region including at least one of a time for a transition to the activity state of the client and a duration for the activity state of the client,
wherein determining an activity state of a region of the cache memory comprises determining the activity state of the region based on the expected activity state of the client.

4 . The method of claim 3 , further comprising selecting a plurality of sections of the region to flush based on an expected time for flushing the plurality of sections being approximately the same as the duration for the activity state,
wherein flushing the region comprises flushing the plurality of sections sequentially.

5 . The method of claim 1 , further comprising determining a flushability status of a second section of the region,
wherein flushing the region comprises flushing the second section based on the flushability status of the second section.

6 . The method of claim 1 , further comprising determining an order for flushing a plurality of sections of the region based on an amount of power saved by powering down each of the plurality of sections,
wherein flushing the region comprises flushing the plurality of sections according to the order for flushing the plurality of sections.

7 . The method of claim 1 , further comprising determining an order for flushing a plurality of sections of the region based on a degree of dirtiness of data stored at each of the plurality of sections,
wherein flushing the region comprises flushing the plurality of sections according to the order for flushing the plurality of sections.

8 . (canceled)

9 . A computing device, comprising:
a cache memory; and a processing device communicatively connected to the cache memory and configured with processor-executable instructions to perform operations comprising:
determining an activity state of a region of the cache memory;
issuing a start cache memory flush command in response to determining that the activity state of the region is idle;
flushing the region in response to the start cache memory flush command;
determining whether the activity state of the region is or is about to be active;
issuing an abort cache memory flush command in response to determining that the activity state of the region is or is about to be active; and
in response to the abort cache memory flush command:
continuing flushing a first section of the region that is undergoing flush; and
aborting flushing the region in response to completing flushing the first section.

10 . The computing device of claim 9 , wherein the processing device is configured with processor-executable instructions to perform operations further comprising receiving an indicator of an activity state of a client associated with the region,
wherein the processing device is configured with processor-executable instructions to perform operations such that determining an activity state of a region of the cache memory comprises determining the activity state of the region based on the activity state of the client.

11 . The computing device of claim 9 , wherein the processing device is configured with processor-executable instructions to perform operations further comprising receiving an indicator of an expected activity state of a client associated with the region including at least one of a time for a transition to the activity state of the client and a duration for the activity state of the client,
wherein the processing device is configured with processor-executable instructions to perform operations such that determining an activity state of a region of the cache memory comprises determining the activity state of the region based on the expected activity state of the client.

12 . The computing device of claim 11 , wherein the processing device is configured with processor-executable instructions to perform operations further comprising selecting a plurality of sections of the region to flush based on an expected time for flushing the plurality of sections being approximately the same as the duration for the activity state,
wherein the processing device is configured with processor-executable instructions to perform operations such that flushing the region comprises flushing the plurality of sections sequentially.

13 . The computing device of claim 9 , wherein the processing device is configured with processor-executable instructions to perform operations further comprising determining a flushability status of a second section of the region,
wherein the processing device is configured with processor-executable instructions to perform operations such that flushing the region comprises flushing the second section based on the flushability status of the second section.

14 . The computing device of claim 9 , wherein the processing device is configured with processor-executable instructions to perform operations further comprising determining an order for flushing a plurality of sections of the region based on an amount of power saved by powering down each of the plurality of sections,
wherein the processing device is configured with processor-executable instructions to perform operations such that flushing the region comprises flushing the plurality of sections according to the order for flushing the plurality of sections.

15 . The computing device of claim 9 , wherein the processing device is configured with processor-executable instructions to perform operations further comprising determining an order for flushing a plurality of sections of the region based on a degree of dirtiness of data stored at each of the plurality of sections,
wherein the processing device is configured with processor-executable instructions to perform operations such that flushing the region comprises flushing the plurality of sections according to the order for flushing the plurality of sections.

16 . (canceled)

17 . A computing device, comprising:
means for determining an activity state of a region of a cache memory; means for issuing a start cache memory flush command in response to determining that the activity state of the region is idle; means for flushing the region in response to the start cache memory flush command; means for determining whether the activity state of the region is or is about to be active; means for issuing an abort cache memory flush command in response to determinin

Assignees

• Qualcomm Inc

Inventors

• Torchalski Andrew
• Jose Edwin
• Stubbs Joshua

Classifications

• G06F2212/1028

  Power efficiency · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title