Generating integrated circuit placements using neural networks conditioned on target reward values
US-2026057164-A1 · Feb 26, 2026 · US
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Jiang Wenjie patents
Jiang Wenjie is listed as an inventor on 25 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Jiang Wenjie |
| Total patents | 25 |
| First publication | May 19, 2016 |
| Latest publication | Feb 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Alignment cost for integrated circuit placement
US-12488164-B2 · Dec 2, 2025 · US
Generating integrated circuit placements using neural networks
US-2025291991-A1 · Sep 18, 2025 · US
Generating integrated circuit placements using neural networks
US-2025124207-A1 · Apr 17, 2025 · US
Generating integrated circuit placements using neural networks
US-12248745-B2 · Mar 11, 2025 · US
Routability-Aware Large-Scale Transistor-Level Placement Using Reinforcement Learning
US-2024394552-A1 · Nov 28, 2024 · US
Generating learned representations of digital circuit designs
US-2024273270-A1 · Aug 15, 2024 · US
Generating integrated circuit placements using neural networks
US-2024249058-A1 · Jul 25, 2024 · US
Alignment Cost for Integrated Circuit Placement
US-2024095424-A1 · Mar 21, 2024 · US
Generating integrated circuit placements using neural networks
US-11853677-B2 · Dec 26, 2023 · US
Recent patents
Latest publications not already listed above.
Assigning routing paths based on interior gateway protocol metric optimization
US-11811614-B2 · Nov 7, 2023 · US
Interior gateway protocol metric optimization
US-2023208720-A1 · Jun 29, 2023 · US
Generating integrated circuit placements using neural networks
US-2023117786-A1 · Apr 20, 2023 · US
Assigning routing paths based on interior gateway protocol metric optimization
US-11601336-B2 · Mar 7, 2023 · US
Generating integrated circuit placements using neural networks
US-11556690-B2 · Jan 17, 2023 · US
Interior Gateway Protocol Metric Optimization
US-2022376984-A1 · Nov 24, 2022 · US
Generating integrated circuit placements using neural networks
US-2022108058-A1 · Apr 7, 2022 · US
Generating integrated circuit placements using neural networks
US-11216609-B2 · Jan 4, 2022 · US
Generating integrated circuit placements using neural networks
US-2021334445-A1 · Oct 28, 2021 · US
Method and apparatus for transferring content among large clusters of storage devices to achieve a target replication distribution
US-9942311-B2 · Apr 10, 2018 · US
Attribution Marketing Recommendations
US-2017345048-A1 · Nov 30, 2017 · US
Parallelized network traffic flow availability simulation using stochastic process and traffic engineering algorithms
US-9705773-B2 · Jul 11, 2017 · US
Attribution marketing recommendations
US-9697534-B2 · Jul 4, 2017 · US
Parallelized network traffic flow availability simulation using stochastic process and traffic engineering algorithms
US-2017012848-A1 · Jan 12, 2017 · US
Method and apparatus for transferring content among large clusters of storage devices to achieve a target replication distribution
US-2016142476-A1 · May 19, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Google Llc | 17 |
| Google Inc | 4 |
| Thomson Licensing | 2 |
| X Dev Llc | 1 |
| Deepmind Tech Ltd | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F30/27 | 15 |
| G06F30/392 | 14 |
| G06N3/09 | 11 |
| G06N3/092 | 11 |
| G06F30/398 | 11 |