Generating integrated circuit placements using neural networks conditioned on target reward values

Patent metadata

Field	Value
Publication number	US-2026057164-A1
Application number	US-202418812871-A
Country	US
Kind code	A1
Filing date	Aug 22, 2024
Priority date	Aug 22, 2024
Publication date	Feb 26, 2026
Grant date	—

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement.

First claim

1 . A method performed by one or more computers, the method comprising:
obtaining netlist data for an integrated circuit chip, wherein the netlist data specifies a connectivity on the integrated circuit chip between a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the integrated circuit chip, and wherein the plurality of nodes comprise macro nodes representing macro components and standard cell nodes representing standard cell components; generating an integrated circuit chip placement that places each node in the netlist data at a respective position on the surface of the integrated circuit chip, comprising:
obtaining a target value of a reward function that measures a quality of the integrated circuit chip placement; and
placing a respective macro node at each of a plurality of time steps according to a macro node order to generate a macro node placement of the macro nodes on the surface of the chip, the placing comprising, for each particular time step in the plurality of time steps:
generating, from the netlist data, an input representation that characterizes at least (i) respective positions on the surface of the chip of any macro nodes that are before a particular macro node to be placed at the particular time step in the macro node order and (ii) the particular macro node to be placed at the particular time step;
processing the input representation and the target value of the reward function using a macro placement neural network having a plurality of network parameters, wherein the macro placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the integrated circuit chip; and
assigning the macro node to be placed at the particular time step to a position from the plurality of positions using the score distribution.

2 . The method of claim 1 , wherein generating the integrated circuit chip placement further comprises:
generating an initial integrated circuit chip placement, comprising placing each of the standard cells at a respective position on the surface of a partially placed integrated circuit chip that includes the macro components represented by the macro nodes placed according to the macro node placement.

3 . The method of claim 1 , wherein the plurality of positions comprise grid squares from an N×M grid overlaid over the surface of the integrated circuit chip.

4 . The method of claim 1 , wherein:
the macro placement neural network includes:
a feature encoding neural network that is configured to:
receive the input representation and process the input representation to generate an encoded representation of the input representation, and
receive the target value of the reward function and process the target value to generate an encoded representation of the target value; and

a policy neural network that is configured to process an input comprising the encoded representation of the input representation and the encoded representation of the target value to generate the score distribution.

5 . The method of claim 4 , wherein the macro placement neural network further comprises:
a value neural network that is configured to process the encoded representation of the input representation to generate a value estimate.

6 . The method of claim 5 , wherein the value neural network is not conditioned on the target value of the reward function.

7 . The method of claim 4 , wherein the input to the policy neural network further comprises visual features that are based on at least (i) the respective positions on the surface of the chip of any macro nodes that are before a particular macro node to be placed at the particular time step in the macro node order and (ii) the particular macro node to be placed at the particular time step.

8 . The method of claim 7 , wherein the visual features comprise an action mask that masks out positions on the surface of the chip that have a density that exceeds a threshold value based on at least the respective positions on the surface of the chip of any macro nodes that are before the particular macro node to be placed at the particular time step in the macro node order.

9 . The method of claim 7 , wherein the visual features comprise a heatmap over the positions on the surface of the chip that represents, for each position, a respective cost of placing the particular macro node at the position given at least the respective positions on the surface of the chip of any macro nodes that are before the particular macro node to be placed at the particular time step in the macro node order.

10 . The method of claim 9 , wherein the respective costs are based on timing paths between macro nodes in the netlist data.

11 . The method of claim 7 , wherein the policy neural network is configured to process the visual features through a convolutional neural network to generate the score distribution, wherein one or more intermediate layers of the convolutional neural network are conditioned on the encoded representations of the target value and the input representation.

12 . The method of claim 1 , wherein the placing comprises, for each of one or more additional time steps in the plurality of time steps:
receiving a user input specifying a placement of a macro node to be placed at the additional time step; and assigning the macro node to be placed at the additional time step to the position specified in the user input.

13 . The method of claim 1 , wherein the macro placement neural network has been trained through supervised learning on a supervised training data set.

14 . The method of claim 13 , wherein, after being trained through supervised learning, the macro placement neural network has been fine-tuned through reinforcement learning on the netlist data.

15 . The method of claim 1 , wherein assigning the node to a position from the plurality of positions using the score distribution comprises:
generating a modified score distribution that sets to zero the score for each position for which a density determined based on the respective positions on the surface of the chip of any macro nodes that are before the particular macro node in the macro node order exceeds a threshold value; and assigning the node using the modified score distribution.

16 . The method of claim 15 , wherein assigning the node using the modified score distribution comprises:
assigning the node to the position having the highest score in the modified score distribution.

17 . The method of claim 15 , wherein assigning the node using the modified score distribution comprises:
sampling a position from the modified score distribution, and assigning the node to the sampled position.

18 . The method of claim 1 , further comprising:
outputting data specifying the integrated circuit chip placement.

19 . The method of claim 18 , wherein outputting data specifying the integrated circuit chip placement comprises outputting the integrated circuit chip placement to a component of an electronic design automation (EDA) software tool.

20 . The method of claim 18 , wherein outputting data specifying the integrated circuit chip placement comprises providing the data specifying the integrated circuit chip placement for presentation to a user on a user device.

21 . The method of claim 18 , wherein outputting data specifying the integrated circuit chip pla

Assignees

• Deepmind Tech Ltd

Inventors

• Guadarrama Cotado Sergio
• Jiang Wenjie
• Zhuang vincent
• Songhori Ebrahim
• Lee Kuang-Huei

Classifications

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F30/323

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G06F30/31

  Design entry, e.g. editors specifically adapted for circuit design · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title