Alignment cost for integrated circuit placement

Patent metadata

Field	Value
Publication number	US-12488164-B2
Application number	US-202217890370-A
Country	US
Kind code	B2
Filing date	Aug 18, 2022
Priority date	Aug 18, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Aspects of the disclosure are directed to automatically determining floor planning in chips, which factors in memory macro alignment. A deep reinforcement learning (RL) agent can be trained to determine optimal placements for the memory macros, where memory macro alignment can be included as a regularization cost to be added to the placement objective as a RL reward. Tradeoffs between the placement objective and alignment of macros can be controlled by a tunable alignment parameter.

First claim

The invention claimed is:

1 . A method for automatically performing floor planning in a chip, the method comprising:
receiving, with one or more processors, data describing a plurality of nodes and connectivity among the plurality of nodes on a surface of the chip, the plurality of nodes comprising one or more blocks of integrated circuit components; identifying, with the one or more processors, a first alignment parameter for positioning the nodes on the surface of the chip based on the data; determining, with the one or more processors, a first reward based on the first alignment parameter; identifying, with the one or more processors, a second alignment parameter for positioning the nodes on the surface of the chip based on the first reward; determining, with the one or more processors, a second reward based on the second alignment parameter; selecting, with the one or more processors, a positioning of the nodes on the surface of the chip based on the second reward; and generating, with the one or more processors, a floor plan for the chip based on the selection.

2 . The method of claim 1 , further comprising iteratively identifying, with the one or more processors, additional alignment parameters for positioning the nodes on the surface of the chip based on a determined reward from a previous iteration.

3 . The method of claim 2 , further comprising iteratively determining, with the one or more processors, additional rewards based on the additional alignment parameters.

4 . The method of claim 3 , further comprising stopping, with the one or more processors, the iterative identifying and determining when the determined rewards approach a convergence or after a predetermined period of time.

5 . The method of claim 1 , further comprising identifying, with the one or more processors, a density parameter and a congestion parameter for positioning the nodes on the surface of the chip.

6 . The method of claim 5 , wherein the first reward is determined further based on the density parameter and congestion parameter.

7 . The method of claim 1 , wherein the determined first and second rewards are determined by a reward function that includes an alignment-based regularization cost.

8 . The method of claim 7 , wherein the alignment-based regularization cost is based on a reverse of a sum of all contiguous areas for the nodes normalized by the number of nodes in the plurality of nodes.

9 . The method of claim 1 , wherein the second alignment parameter is identified to increase a likelihood that the second reward is greater than the first reward.

10 . A system comprising:
one or more processors; and one or more storage devices coupled to the one or more processors and storing instructions that, when executed by the one or more processors, causes the one or more processors to perform operations for automatically performing floor planning in a chip, the operations comprising:
receiving data describing a plurality of nodes and connectivity among the plurality of nodes on a surface of the chip, the plurality of nodes comprising one or more blocks of integrated circuit components;
identifying a first alignment parameter for positioning the nodes on the surface of the chip based on the data;
determining a first reward based on the first alignment parameter;
identifying a second alignment parameter for positioning the nodes on the surface of the chip based on the first reward;
determining a second reward based on the second alignment parameter;
selecting a positioning of the nodes on the surface of the chip based on the second reward; and
generating a floor plan for the chip based on the selection.

11 . The system of claim 10 , wherein the operations further comprise:
iteratively identifying additional alignment parameters for positioning the nodes on the surface of the chip based on a determined reward from a previous iteration; iteratively determining additional rewards based on the additional alignment parameters; and stopping the iterative identifying and determining when the determined rewards approach a convergence or after a predetermined period of time.

12 . The system of claim 10 , wherein the operations further comprise identifying a density parameter and a congestion parameter for positioning the nodes on the surface of the chip, the first reward being determined further based on the density parameter and congestion parameter.

13 . The system of claim 10 , wherein the determined first and second rewards are determined by a reward function that includes an alignment-based regularization cost.

14 . The system of claim 13 , wherein the alignment-based regularization cost is based on a reverse of a sum of all contiguous areas for the nodes normalized by the number of nodes in the plurality of nodes.

15 . The system of claim 10 , wherein the second alignment parameter is identified to increase a likelihood that the second reward is greater than the first reward.

16 . A non-transitory computer readable medium for storing instructions that, when executed by one or more processors, causes the one or more processors to perform operations for automatically performing floor planning in a chip, the operations comprising:
receiving data describing a plurality of nodes and connectivity among the plurality of nodes on a surface of the chip, the plurality of nodes comprising one or more blocks of integrated circuit components; identifying a first alignment parameter for positioning the nodes on the surface of the chip based on the data; determining a first reward based on the first alignment parameter; identifying a second alignment parameter for positioning the nodes on the surface of the chip based on the first reward; determining a second reward based on the second alignment parameter; selecting a positioning of the nodes on the surface of the chip based on the second reward; and generating a floor plan for the chip based on the selection.

17 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise:
iteratively identifying additional alignment parameters for positioning the nodes on the surface of the chip based on a determined reward from a previous iteration; iteratively determining additional rewards based on the additional alignment parameters; and stopping the iterative identifying and determining when the determined rewards approach a convergence or after a predetermined period of time.

18 . The non-transitory computer readable medium of claim 16 , wherein the operations further comprise identifying a density parameter and a congestion parameter for positioning the nodes on the surface of the chip, the first reward being determined further based on the density parameter and congestion parameter.

19 . The non-transitory computer readable medium of claim 16 , wherein the determined first and second rewards are determined by a reward function that includes an alignment-based regularization cost, the alignment-based regularization cost being based on a reverse of a sum of all contiguous areas for the nodes normalized by the number of nodes in the plurality of nodes.

20 . The non-transitory computer readable medium of claim 16 , wherein the second alignment parameter is identified to increase a likelihood that the second reward is greater than the first reward.

Assignees

• Google Llc

Inventors

• Songhori Ebrahim Mohammadgholi
• Wang Shen
• Mirhoseini Azalia
• Goldie Anna
• Carpenter Roger
• Jiang Wenjie
• Lee Young-Joon
• Laudon James

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/27 Primary

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title